{"title":"FPGA Based Controller of BLDC Motor Using Trapezoid Control","authors":"Nurul Hidayat, Faizal Arya Samman, R. Sadjad","doi":"10.1109/ICITEE56407.2022.9954075","DOIUrl":null,"url":null,"abstract":"This paper presents the design of digital control based on FPGA to control the speed of a brushless direct current (BLDC) motor. The control algorithm applies trapezoid control or six-step commutation and unipolar independent PWM switching the commutation itself depends on three built-in hall effect sensors. This method is implemented on FPGA using a state machine model. Besides the speed control algorithm, this paper also presents an algorithm to calculate the speed of the BLDC motor. The speed calculation builds up with a counter to count the electric cycles for one second then the result is stored in the register and lookup table to convert the electric cycles data into revolutions per minute (rpm) data. The speed control and speed calculation are written using Verilog hardware description language (HDL) and verified through simulation using ModelSim the code is implemented on the FPGA DEO-nano EP4CE22 board. Motor control testing was carried out on a 350-watt 36 v BLDC motor with a three-phase inverter as the driver. The results are that the BLDC motor can rotate at maximum speed without and with a load of 3 kg, namely 699 RPM and 668 RPM respectively, for rotating clockwise and counterclockwise","PeriodicalId":246279,"journal":{"name":"2022 14th International Conference on Information Technology and Electrical Engineering (ICITEE)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 14th International Conference on Information Technology and Electrical Engineering (ICITEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICITEE56407.2022.9954075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the design of digital control based on FPGA to control the speed of a brushless direct current (BLDC) motor. The control algorithm applies trapezoid control or six-step commutation and unipolar independent PWM switching the commutation itself depends on three built-in hall effect sensors. This method is implemented on FPGA using a state machine model. Besides the speed control algorithm, this paper also presents an algorithm to calculate the speed of the BLDC motor. The speed calculation builds up with a counter to count the electric cycles for one second then the result is stored in the register and lookup table to convert the electric cycles data into revolutions per minute (rpm) data. The speed control and speed calculation are written using Verilog hardware description language (HDL) and verified through simulation using ModelSim the code is implemented on the FPGA DEO-nano EP4CE22 board. Motor control testing was carried out on a 350-watt 36 v BLDC motor with a three-phase inverter as the driver. The results are that the BLDC motor can rotate at maximum speed without and with a load of 3 kg, namely 699 RPM and 668 RPM respectively, for rotating clockwise and counterclockwise