C. Kuo, E. Yang, W. Wong, C. Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, L. Kuo, Shi-Hsien Chen, Houng-Chi Wei, H. Hwang, S. Pittikoun
{"title":"A New Self-Aligned NAND Type SONOS Flash Memory with High Scaling Abilities, Fast Programming/Erase Speeds and Good Data Retention Performances","authors":"C. Kuo, E. Yang, W. Wong, C. Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, L. Kuo, Shi-Hsien Chen, Houng-Chi Wei, H. Hwang, S. Pittikoun","doi":"10.1109/NVMT.2006.378868","DOIUrl":null,"url":null,"abstract":"In this paper, we will propose a new NAND type SONOS cell structure with high efficiency Source Side Injection programming and F-N erase. This cell is characterized in high scaling abilities, fast program/erase speeds and very satisfactory data retention performances. In consideration of the threshold voltage saturation of the SONOS cell during erase, we use the modified erase bias configuration, DSPE (decrement step pulse erase), to speed up the erase operation and enlarge the memory window without adding any process complexities. To further improve the erase speed, p+-poly gate has firstly been utilized on our NAND type SONOS cell. From our experimental results, p+-poly gate not only prolongs erase threshold voltage saturation to the longer time but improves charge loss characteristics. Instead of traditional threshold voltage extrapolations from short to long time, we applied the time constant model to predict concrete threshold voltage values with various baking time and temperatures.","PeriodicalId":263387,"journal":{"name":"2006 7th Annual Non-Volatile Memory Technology Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 7th Annual Non-Volatile Memory Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMT.2006.378868","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, we will propose a new NAND type SONOS cell structure with high efficiency Source Side Injection programming and F-N erase. This cell is characterized in high scaling abilities, fast program/erase speeds and very satisfactory data retention performances. In consideration of the threshold voltage saturation of the SONOS cell during erase, we use the modified erase bias configuration, DSPE (decrement step pulse erase), to speed up the erase operation and enlarge the memory window without adding any process complexities. To further improve the erase speed, p+-poly gate has firstly been utilized on our NAND type SONOS cell. From our experimental results, p+-poly gate not only prolongs erase threshold voltage saturation to the longer time but improves charge loss characteristics. Instead of traditional threshold voltage extrapolations from short to long time, we applied the time constant model to predict concrete threshold voltage values with various baking time and temperatures.