Improving timing error tolerance without impact on chip area and power consumption

Abstract

The demand of power saving and highly dependable LSI has increased by the miniaturization of device process technology and the spread of portable devices such as mobile phones. The design method which takes the worst case scenario makes the design margin too large because of the parameter variations in the deep submicron domain and it has serious impact for performance and power consumption. To deal with excessive design margins, typical-case design method with canary FF has been proposed so far. By using canary FF, variability-aware large guard band can be decreased. In this paper, we describe how canary FF can be integrated in a typical digital circuit design flow in detail and analyze the area and power overheads compared with the worst-case design method. The analysis is done by implementing two conventional 32-bit RISC processor cores; miniMIPS and MeP (Media Embedded Processor). The results show that our proposed method can reduce chip areas effectively and power overhead can be reduced to very small.