Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model

Abstract

Gate sizing is one of the most important techniques for circuit optimization. Over the years, Elmore delay model (EDM) has been the predominant timing model used in gate sizing due to its simplicity. However, EDM is no longer effective in meeting the increasing demand of timing accuracy. In this paper, we propose a new gate delay model, which characterizes the timing information of lookup tables and creates a model which is mathematically similar to EDM, and can be easily incorporated into well-known EDM based gate sizing techniques using Lagrangian Relaxation (LR) with minor modifications. Experimental data show that it can produce even better results than those directly based on lookup tables, while keeping the benefit of the simplicity of EDM.