A 0.7 – 3.7 GHz six phase receiver front-end with third order harmonic rejection

Anders Nejdel, Markus Törmänen, H. Sjöland
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引用次数: 9

Abstract

This paper presents a highly linear receiver front-end operating from 700 MHz to 3.7 GHz with 3rd order harmonic rejection. It consists of a complementary low noise transconductance amplifier with capacitive cross coupling and negative gm current sources, a six phase current-mode passive mixer, and baseband transimpedance amplifiers providing programmable gain. The circuit has been fabricated in 65 nm CMOS technology with an active area of just 0.09 mm2. It consumes 7.2 mA, excluding the six phase local oscillator generation, from a 1.2 V supply, achieving a third order harmonic rejection of 40 dB, and a noise figure of 3 to 4.5 dB at 52 dB gain. The out of band IIP2 and IIP3 at full gain is +55 dBm and +5 dBm, respectively.
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具有三阶谐波抑制的0.7 - 3.7 GHz六相接收机前端
本文提出了一种工作频率为700 MHz ~ 3.7 GHz的三阶谐波抑制型高线性接收机前端。它包括一个互补的低噪声跨导放大器,具有电容交叉耦合和负通用电流源,一个六相电流模式无源混频器,以及提供可编程增益的基带跨阻放大器。该电路采用65纳米CMOS技术制造,有效面积仅为0.09 mm2。它的功耗为7.2 mA(不包括六相本振产生),来自1.2 V电源,在52 dB增益下实现了40 dB的三阶谐波抑制和3至4.5 dB的噪声系数。带外IIP2和IIP3在全增益时分别为+55 dBm和+5 dBm。
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