Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors

Abstract

For efficient use of the upcoming Stacked Gate-all-around Nanosheet Field Effect Transistors (GAAFET), identifying and mitigating leakage current components are essential. This paper comprehensively investigates the leakage components not only in the nanosheets but also through the substrate, including effects such as Gate-Induced Drain Lowering (GIDL) and parasitic substrate leakage. We thoroughly investigate the impact of device geometry on the device leakage current and propose device design guidelines for mitigation of the substrate leakage current for these devices. In addition, we have modeled the GIDL current of GAAFETs using BSIM-CMG code.