Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117608
S. Manikandan, Nitanshu Chauhan, N. Bagga, Abhishek Kumar, Shashank Banchhor, Sourajeet Roy, A. Bulusu, A. Dasgupta, S. Dasgupta
For efficient use of the upcoming Stacked Gate-all-around Nanosheet Field Effect Transistors (GAAFET), identifying and mitigating leakage current components are essential. This paper comprehensively investigates the leakage components not only in the nanosheets but also through the substrate, including effects such as Gate-Induced Drain Lowering (GIDL) and parasitic substrate leakage. We thoroughly investigate the impact of device geometry on the device leakage current and propose device design guidelines for mitigation of the substrate leakage current for these devices. In addition, we have modeled the GIDL current of GAAFETs using BSIM-CMG code.
{"title":"Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors","authors":"S. Manikandan, Nitanshu Chauhan, N. Bagga, Abhishek Kumar, Shashank Banchhor, Sourajeet Roy, A. Bulusu, A. Dasgupta, S. Dasgupta","doi":"10.1109/ICEE56203.2022.10117608","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117608","url":null,"abstract":"For efficient use of the upcoming Stacked Gate-all-around Nanosheet Field Effect Transistors (GAAFET), identifying and mitigating leakage current components are essential. This paper comprehensively investigates the leakage components not only in the nanosheets but also through the substrate, including effects such as Gate-Induced Drain Lowering (GIDL) and parasitic substrate leakage. We thoroughly investigate the impact of device geometry on the device leakage current and propose device design guidelines for mitigation of the substrate leakage current for these devices. In addition, we have modeled the GIDL current of GAAFETs using BSIM-CMG code.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121125313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118301
A. Sahu, Abhishek Kumar, Anurag Dwivedi, S. P. Tiwari
The performance of thin body doping-free bipolar transistors on SOI are demonstrated for logic gates circuit using differential pass transistor logic. Charge carriers are induced inside the lightly doped SOI layer by using charge plasma (CP) and polarity control (PC) approaches. The study analyzes the transient, power, and noise margins of logic gates i.e., AND, OR and XOR gates designed using four device configurations i.e., CP based npn, CP based pnp, PC based npn, and PC based pnp. The results of these analyses are compared to prior studies of doping-free device-based circuits. The transient analysis indicates rise and fall time less than 50 ps and average switching power less than 5 µ W. The worstcase noise margin observed for 1 V input level is 0.28 V. Additionally, a 2:1 multiplexer is also designed and examined for response time and output voltage levels. For high logic, worst case output was 0.88 V, while for low logic, it was 0.05 V. The multiplexer took less than 1.8 ns to produce the output.
{"title":"Thin Body Doping-free Bipolar Transistors: A Performance Projection at Circuits Level","authors":"A. Sahu, Abhishek Kumar, Anurag Dwivedi, S. P. Tiwari","doi":"10.1109/ICEE56203.2022.10118301","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118301","url":null,"abstract":"The performance of thin body doping-free bipolar transistors on SOI are demonstrated for logic gates circuit using differential pass transistor logic. Charge carriers are induced inside the lightly doped SOI layer by using charge plasma (CP) and polarity control (PC) approaches. The study analyzes the transient, power, and noise margins of logic gates i.e., AND, OR and XOR gates designed using four device configurations i.e., CP based npn, CP based pnp, PC based npn, and PC based pnp. The results of these analyses are compared to prior studies of doping-free device-based circuits. The transient analysis indicates rise and fall time less than 50 ps and average switching power less than 5 µ W. The worstcase noise margin observed for 1 V input level is 0.28 V. Additionally, a 2:1 multiplexer is also designed and examined for response time and output voltage levels. For high logic, worst case output was 0.88 V, while for low logic, it was 0.05 V. The multiplexer took less than 1.8 ns to produce the output.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126180953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118265
P. Thakur, T. N. Narayanan
Utilizing a diverse mix of batteries in electric vehicles (EVs) is estimated to boost the transition to clean and fossil-free cost-effective transportation. This discussion is mainly on the advancement of a ‘next-generation’ energy storage system called- Metal-Air Batteries (MABs) by overcoming various performance-limiting issues related to their electrodes and electrolytes, where MABs are identified as one of the important elements of next-generation traction. This study highlights the significance of engineering the electrodes and electrolytes for improving the cyclability of MABs with low overpotential for charging. Different strategies set out here open a plethora of new routes in designing high-performance MAB systems by simple tweaking of electrodes/electrolytes.
{"title":"Towards Advanced Rechargeable Metal (Zn, Li)-air (O2) Battery Systems Using Electrode and Electrolyte Engineering","authors":"P. Thakur, T. N. Narayanan","doi":"10.1109/ICEE56203.2022.10118265","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118265","url":null,"abstract":"Utilizing a diverse mix of batteries in electric vehicles (EVs) is estimated to boost the transition to clean and fossil-free cost-effective transportation. This discussion is mainly on the advancement of a ‘next-generation’ energy storage system called- Metal-Air Batteries (MABs) by overcoming various performance-limiting issues related to their electrodes and electrolytes, where MABs are identified as one of the important elements of next-generation traction. This study highlights the significance of engineering the electrodes and electrolytes for improving the cyclability of MABs with low overpotential for charging. Different strategies set out here open a plethora of new routes in designing high-performance MAB systems by simple tweaking of electrodes/electrolytes.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122542271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117977
Apoorva Singh, Bidisha Nath, A. Panchal, Praveen C Ramamurthy
Tin oxide (SnO2) is one of the important and commonly used electron transfer layers (ETLs) in the planar structure of perovskite solar cells (PSCs). Doping the SnO2 layer with chlorinated salts such as potassium chloride (KCl) has been reported to improve the power conversion efficiency (PCE), intriguing further exploration of other chlorinated salts. Herein, the results from various chlorinated salts in addition to KCl are evaluated. It was observed, that though the PSCs with KCl doped SnO2 layer yield the best PCE (~17%), the ETL layer doped with other chlorinated salts such as sodium chloride (NaCl) and Iron chloride (FeCl3) also showed improvement in performance from the pristine SnO2 (~15 %). Moreover, the results from the SnO2-NaCl-based devices are found to be comparable to the SnO2-KCl. Performance enhancement is attributed to the passivation of defects in the interface and reduction in the non-radiative recombination losses. The established trend is supported by the current-voltage (J-V) and photoluminescence (PL) studies.
{"title":"Performance enhancement by introducing different chlorinated salts in the SnO2 electron transfer layer of perovskite solar cells","authors":"Apoorva Singh, Bidisha Nath, A. Panchal, Praveen C Ramamurthy","doi":"10.1109/ICEE56203.2022.10117977","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117977","url":null,"abstract":"Tin oxide (SnO2) is one of the important and commonly used electron transfer layers (ETLs) in the planar structure of perovskite solar cells (PSCs). Doping the SnO2 layer with chlorinated salts such as potassium chloride (KCl) has been reported to improve the power conversion efficiency (PCE), intriguing further exploration of other chlorinated salts. Herein, the results from various chlorinated salts in addition to KCl are evaluated. It was observed, that though the PSCs with KCl doped SnO2 layer yield the best PCE (~17%), the ETL layer doped with other chlorinated salts such as sodium chloride (NaCl) and Iron chloride (FeCl3) also showed improvement in performance from the pristine SnO2 (~15 %). Moreover, the results from the SnO2-NaCl-based devices are found to be comparable to the SnO2-KCl. Performance enhancement is attributed to the passivation of defects in the interface and reduction in the non-radiative recombination losses. The established trend is supported by the current-voltage (J-V) and photoluminescence (PL) studies.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"45 13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122888498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117821
A. V. N. Devi, P. N. S. Bhargav, S. Khandelwal, V. Gurugubelli, S. Karmalkar
We examine two widely prevalent parameter extraction methodologies for Schottky contacts, namely, Regional and Cheung-Cheung's methods. We establish that the Cheung-Cheung's method is highly effective for barrier heights greater than 0.4 V, but fails for low barrier heights. Further, we examine the thermionic emission (TE) models employed by ATLAS and SENTAURUS simulators. We show that the default TE model in ATLAS, called THERM, is not the right choice but the surface recombination velocity-based models are to be used. The Cheung-Cheung's method, when applied to the simulated data for Schottky contacts on Si and GaN, extracts much different barrier height and ideality factor when the input barrier height is small and series resistance is large.
{"title":"Numerical Simulation and Parameter Extraction of Pure Thermionic Emission Across Schottky Contacts","authors":"A. V. N. Devi, P. N. S. Bhargav, S. Khandelwal, V. Gurugubelli, S. Karmalkar","doi":"10.1109/ICEE56203.2022.10117821","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117821","url":null,"abstract":"We examine two widely prevalent parameter extraction methodologies for Schottky contacts, namely, Regional and Cheung-Cheung's methods. We establish that the Cheung-Cheung's method is highly effective for barrier heights greater than 0.4 V, but fails for low barrier heights. Further, we examine the thermionic emission (TE) models employed by ATLAS and SENTAURUS simulators. We show that the default TE model in ATLAS, called THERM, is not the right choice but the surface recombination velocity-based models are to be used. The Cheung-Cheung's method, when applied to the simulated data for Schottky contacts on Si and GaN, extracts much different barrier height and ideality factor when the input barrier height is small and series resistance is large.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114163500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118140
Nehru Devabharathi, J. R. Pradhan, S. Dasgupta
Oxide semiconductors are increasingly becoming the material of choice in the emerging printed and flexible electronics domain. While they have attracted tremendous research attention in the area of solution processed/printed electronics, the vacuum deposited amorphous oxide semiconductor TFTs have also achieved serious commercial success in the transparent and curved display industries. Nonetheless, it may be noted that although the n-type oxides demonstrate excellent electronic transport, the performance of the hole conducting p-type oxides are still unsatisfactory and thus it affects the fabrication of all oxide complementary metal oxide semiconductor (CMOS) circuits. In order to resolve the issue, unipolar depletion-load type pseudo-CMOS inverters have recently been proposed. In this regard, here, we demonstrate a co-continuous mesoporous indium oxide based thin film transistor (TFT) technology with edge-FET architecture and near vertical transport. At the next step, high performance, unipolar depletion-load type inverters have been fabricated using these edge-FET TFTs. The fabricated TFTs have shown average ON-current of 1.95 mA alongside excellent On/Off ratio (>107). On the other hand, the depletion-load type inverters have demonstrated sharp voltage transfer characteristics (VTC) with a maximum signal gain of 58 at VDD= 2 V, supply voltage.
{"title":"Inkjet-printed mesoporous indium oxide-based near-vertical transport thin film transistors and pseudo-CMOS inverters","authors":"Nehru Devabharathi, J. R. Pradhan, S. Dasgupta","doi":"10.1109/ICEE56203.2022.10118140","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118140","url":null,"abstract":"Oxide semiconductors are increasingly becoming the material of choice in the emerging printed and flexible electronics domain. While they have attracted tremendous research attention in the area of solution processed/printed electronics, the vacuum deposited amorphous oxide semiconductor TFTs have also achieved serious commercial success in the transparent and curved display industries. Nonetheless, it may be noted that although the n-type oxides demonstrate excellent electronic transport, the performance of the hole conducting p-type oxides are still unsatisfactory and thus it affects the fabrication of all oxide complementary metal oxide semiconductor (CMOS) circuits. In order to resolve the issue, unipolar depletion-load type pseudo-CMOS inverters have recently been proposed. In this regard, here, we demonstrate a co-continuous mesoporous indium oxide based thin film transistor (TFT) technology with edge-FET architecture and near vertical transport. At the next step, high performance, unipolar depletion-load type inverters have been fabricated using these edge-FET TFTs. The fabricated TFTs have shown average ON-current of 1.95 mA alongside excellent On/Off ratio (>107). On the other hand, the depletion-load type inverters have demonstrated sharp voltage transfer characteristics (VTC) with a maximum signal gain of 58 at VDD= 2 V, supply voltage.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114362298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118175
Abhishek Kumar, G. Pahwa, A. Behera, A. Bulusu, S. Mehrotra, A. Dasgupta
This paper presents an in-depth analysis of the flicker noise (1/f noise) in Field Effect Transistors (FETs) with ferroelectric gate stack. The analysis is valid for all ferroelectric FETs (FeFETs). We have also proposed an enhancement to industry standard flicker noise models to take ferroelectric thickness into account.
{"title":"Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs","authors":"Abhishek Kumar, G. Pahwa, A. Behera, A. Bulusu, S. Mehrotra, A. Dasgupta","doi":"10.1109/ICEE56203.2022.10118175","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118175","url":null,"abstract":"This paper presents an in-depth analysis of the flicker noise (1/f noise) in Field Effect Transistors (FETs) with ferroelectric gate stack. The analysis is valid for all ferroelectric FETs (FeFETs). We have also proposed an enhancement to industry standard flicker noise models to take ferroelectric thickness into account.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122061290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117762
Barnali Mahato, Prajit Kumar Das, A. Bhardwaj
We report the synthesis of high-quality, non-toxic, highly emitting InP/ZnS core-shell QDs. The QDs exhibit photoluminescence that is temperature dependent. A planar configuration of QDs has been used to fabricate a temperature sensor.
{"title":"InP /ZnS core shell quantum dots as temperature sensor","authors":"Barnali Mahato, Prajit Kumar Das, A. Bhardwaj","doi":"10.1109/ICEE56203.2022.10117762","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117762","url":null,"abstract":"We report the synthesis of high-quality, non-toxic, highly emitting InP/ZnS core-shell QDs. The QDs exhibit photoluminescence that is temperature dependent. A planar configuration of QDs has been used to fabricate a temperature sensor.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116756296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10118163
S. Verma, Bhaskar Mitra
This study explores the correlation between indirect and direct deflection measurement techniques for MEMS actuators. The measured airgap capacitance is used to calculate deflection using parallel plate model and FEM extracted model for indirect technique. Direct device deflection is measured using an optical profilometer. A 110 µm long and 2.5 µm thick Si-folded cantilever beam with 460 nm airgap electrostatic actuation is used for the measurement. The characterization shows that the device pre-pull-in deflection is up to 98 nm for 4V range with both the methods. The calculated data demonstrate that, in contrast to the parallel plate, which has a 12.7% mean square error, the FEM calibrated model agrees with profilometer to within 8.6% for pre-pull-in deflection.
{"title":"Measurement of MEMS Actuator Deflection by C-V Method","authors":"S. Verma, Bhaskar Mitra","doi":"10.1109/ICEE56203.2022.10118163","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10118163","url":null,"abstract":"This study explores the correlation between indirect and direct deflection measurement techniques for MEMS actuators. The measured airgap capacitance is used to calculate deflection using parallel plate model and FEM extracted model for indirect technique. Direct device deflection is measured using an optical profilometer. A 110 µm long and 2.5 µm thick Si-folded cantilever beam with 460 nm airgap electrostatic actuation is used for the measurement. The characterization shows that the device pre-pull-in deflection is up to 98 nm for 4V range with both the methods. The calculated data demonstrate that, in contrast to the parallel plate, which has a 12.7% mean square error, the FEM calibrated model agrees with profilometer to within 8.6% for pre-pull-in deflection.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129851510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-11DOI: 10.1109/ICEE56203.2022.10117691
B. Nayak, S. Chakraborty, Rajdeep Banerjee, Purbasha Ray, Baisali Kundu, S. Bisoyi, R. Basori, Gopal K. Pradhan, D. Goswami, P. Sahoo
We reported the direct growth of electronic grade 2D Mos2- Ws2lateral heterostructures (LHS) by controlling critical physicochemical parameters using a water-assisted chemical vapor deposition technique. Raman and photoluminescence spectroscopy and transport measurements were used to standardize their optical and electronic characteristics. In addition, the role of metal contacts in the transport characteristics in the field-effect transistor geometry of the LHS was evaluated.
{"title":"Edge-epitaxial Growth of Mos2- Ws2lateral heterostructure and their optoelectronic properties","authors":"B. Nayak, S. Chakraborty, Rajdeep Banerjee, Purbasha Ray, Baisali Kundu, S. Bisoyi, R. Basori, Gopal K. Pradhan, D. Goswami, P. Sahoo","doi":"10.1109/ICEE56203.2022.10117691","DOIUrl":"https://doi.org/10.1109/ICEE56203.2022.10117691","url":null,"abstract":"We reported the direct growth of electronic grade 2D Mos2- Ws2lateral heterostructures (LHS) by controlling critical physicochemical parameters using a water-assisted chemical vapor deposition technique. Raman and photoluminescence spectroscopy and transport measurements were used to standardize their optical and electronic characteristics. In addition, the role of metal contacts in the transport characteristics in the field-effect transistor geometry of the LHS was evaluated.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128511490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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