High Level Test Generation / SW based Embedded Test

Abstract

As device geometries scale, product complexity has increased with more and more functionality embedded into integrated chips in recent times. In the processor domain, multiple cores with associated glue logic and cache all on a single die are becoming more and more popular. At the same time, product frequencies have gone up and the need to test for delay defects and marginal circuits is rising continually. This is exacerbated in recent times with the focus on lowpower design. While there has been a lot of progress in scan based delay test, the reliance on functional tests has continued. The biggest concern with scan test effectiveness is related to screening small delay defects. Gross delay defects can be tested using a good set of scan transition fault tests (scan AC tests). However questions remain with respect to the effectiveness of scan tests to screen small delay defects and also to test marginality related failures: for example, speed failures caused by issues like cross-capacitance, power droop etc. Functional tests are being used today for getting the last few DPM to reach quality goals. The reliance on functional tests is higher in products that push the process/design envelope to reach performance/power goals.