VHDL-AMS Model Creation

Abstract

In analog and mixed-signal design, there is a growing interest to move away from proprietary modelling languages and to adopt a market standard, such as VHDL-AMS (IEEE 1076.1999). But many questions still remain about the risk of the migration path. Is there any possibility to convert directly the existing models, or is it necessary to rebuild the library? How much effort and expertise will be needed? In this paper, we try to answer to some of those concerns. We will explore the possible methodologies for generating VHDL-AMS model from other hardware description languages (HDL). Firstly, we focus on how to create a model based on the available information. In a second part, we investigate the automation tools available which can be used. Finally, we share our experience in converting a MAST amplifier model, coming from our research laboratory, to VHDL-AMS