Embedded memory reliability: the SER challenge

Abstract

Drastic decreases in device dimensions and power supply have significantly reduced noise margins and challenged the reliability of very deep-submicron chips. Soft error rate is the main cause behind this challenge. Even though both logic block and embedded memories are impacted by this challenge, but the failure rate in embedded memories remains dominant and requires infrastructure IP for self-correctness. ECC is such an IP. It operates in the field during normal mode operation of a chip. The infrastructure IP in this case need to be fully integrated with the functional memory IP. This allows for timing and area optimization and provides protection throughout the life cycle. This work discusses the growing SER challenge and discusses the integrated IP approach to help resolve it.