A novel method for silicon configurable test flow and algorithms for testing, debugging and characterizing different types of embedded memories through a shared controller

Abstract

In present day system-on-chips (SOC), a large part (/spl sim/70%) is occupied by memories. The overall yield of the SoC relies heavily on the memory yield. To minimize the test and diagnosis effort, we present a system for silicon configurable test flow and algorithms for different types of memories including multi-port memories, through a shared controller. It supports manufacturing tests as well as diagnosis and electrical AC characterisation of memories. With low area overhead, the proposed microcode based configurable controller gives the test engineer freedom to do complete testing on-chip with few micro-codes.