Low power and compact mixed-mode signal processing hardware using spin-neurons

M. Sharad, Deliang Fan, K. Roy
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引用次数: 3

Abstract

CMOS Digital signal processing hardware are power efficient but consume large area, whereas, analog processing units, based on CMOS technology are compact, but power hungry. Emerging magneto-metallic spin-torque devices like domain wall magnets can however perform analog-mode computation like summation and thresholding at ultra low voltage. Such devices can be exploited in designing spin-CMOS hybrid analog processing units that are compact as well as low power. In this work we present a mixed-mode signal processing scheme employing “domain wall neurons” that involves energy efficient analog-mode computation upon digital data. Simulation results for 8-bit, 16-tap FIR filter show that such a design can achieve 10x lower power consumption and 16x lower area as compared to an optimized digital CMOS design at the same technology node. In such a design area saving can be traded off for enhanced power savings, depending upon the target application.
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使用自旋神经元的低功耗和紧凑的混合模式信号处理硬件
数字信号处理硬件节能,但占用面积大,而基于CMOS技术的模拟处理单元紧凑,但耗电大。然而,新兴的磁金属自旋力矩器件,如畴壁磁体,可以在超低电压下进行模拟模式计算,如求和和阈值。这种器件可用于设计紧凑和低功耗的自旋- cmos混合模拟处理单元。在这项工作中,我们提出了一种采用“域壁神经元”的混合模式信号处理方案,该方案涉及对数字数据进行节能模拟模式计算。对8位16分接FIR滤波器的仿真结果表明,在相同的技术节点上,与优化的数字CMOS设计相比,这种设计可以实现低10倍的功耗和低16倍的面积。在这样的设计领域中,根据目标应用程序的不同,可以用节省来换取增强的电力节省。
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