D. Juang, De-Sheng Chen, Jyou-Min Shyu, Ching-Yuang Wu
{"title":"A low-power 1.2 GHz 0.35 /spl mu/m CMOS PLL","authors":"D. Juang, De-Sheng Chen, Jyou-Min Shyu, Ching-Yuang Wu","doi":"10.1109/APASIC.2000.896918","DOIUrl":null,"url":null,"abstract":"In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35 /spl mu/m TSMC CMOS technology. The total power consumption is 9.6 mW at 1.2-GHz operating frequency with 1.5 V supply voltage. The phase noise is -94 dBc at 10 kHz offset.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896918","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35 /spl mu/m TSMC CMOS technology. The total power consumption is 9.6 mW at 1.2-GHz operating frequency with 1.5 V supply voltage. The phase noise is -94 dBc at 10 kHz offset.
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