{"title":"SystemVerilog for VHDL users","authors":"T. Fitzpatrick","doi":"10.1109/DATE.2004.1269080","DOIUrl":null,"url":null,"abstract":"SystemVerilog was developed to provide an evolutionary path from existing hardware description languages (HDLs) to next-generation design and verification methodologies necessary to support the development of the increasingly complex SoC designs of today and tomorrow. Although its roots are firmly planted in Verilog, many of the features of SystemVerilog were targeted to address capabilities that VHDL users have had for years. This tutorial will provide an overview of SystemVerilog, focusing on those language features that enable the adoption of SystemVerilog by VHDL designers, such as complex and user-defined data types, multi-dimensional arrays, and the concept of strong data type checking. In addition, we will show how VHDL and Verilog users can take advantage of distinct SystemVerilog features to improve their productivity with advanced coding capability and built-in verification.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.2004.1269080","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

SystemVerilog was developed to provide an evolutionary path from existing hardware description languages (HDLs) to next-generation design and verification methodologies necessary to support the development of the increasingly complex SoC designs of today and tomorrow. Although its roots are firmly planted in Verilog, many of the features of SystemVerilog were targeted to address capabilities that VHDL users have had for years. This tutorial will provide an overview of SystemVerilog, focusing on those language features that enable the adoption of SystemVerilog by VHDL designers, such as complex and user-defined data types, multi-dimensional arrays, and the concept of strong data type checking. In addition, we will show how VHDL and Verilog users can take advantage of distinct SystemVerilog features to improve their productivity with advanced coding capability and built-in verification.
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SystemVerilog为VHDL用户
SystemVerilog的开发旨在提供从现有硬件描述语言(hdl)到下一代设计和验证方法的进化路径,以支持当今和未来日益复杂的SoC设计的开发。尽管SystemVerilog的根基牢固地植根于Verilog,但它的许多特性都是针对VHDL用户多年来一直拥有的功能。本教程将提供SystemVerilog的概述,重点介绍那些使VHDL设计人员能够采用SystemVerilog的语言特性,例如复杂和用户定义的数据类型、多维数组以及强数据类型检查的概念。此外,我们将展示VHDL和Verilog用户如何利用不同的SystemVerilog特性,通过先进的编码能力和内置验证来提高他们的生产力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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