Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268807
A. Ripp, R. Sommer, E. Hennig, M. Pronath
Summary form only given, as follows. The tutorial presents an introduction into "DfY/DfM - Design for Yield and Manufacturability" covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment. Intended audience: analogue- and mixed-signal circuit designers, CAD- and design-support engineers (library management, technology migration and design reuse, process characterisation)
{"title":"DFY/DFM - design for yield and manufacturability (industrial tutorial)","authors":"A. Ripp, R. Sommer, E. Hennig, M. Pronath","doi":"10.1109/DATE.2004.1268807","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268807","url":null,"abstract":"Summary form only given, as follows. The tutorial presents an introduction into \"DfY/DfM - Design for Yield and Manufacturability\" covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment. Intended audience: analogue- and mixed-signal circuit designers, CAD- and design-support engineers (library management, technology migration and design reuse, process characterisation)","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125538506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268810
W. Najjar, F. Kurdahi, K. Vissers
Addresses modelling for analysis and optimisation of MPSoC architectures including hardware and software layers such as drivers, run-time systems and application APIs. Different scheduling strategies, communication behaviours and performance requirements must be matched and combined on a single system. 4. Presents the DELI experience to show that application level software development can be overlapped with the development of the rest of the system. DELI is aimed to generating portable HdS taking into account real-time constraints and low-level interactions with OS and the HW during early prototyping. Platforms that combine CPUs with a reconfigurable fabric on the same chip have been recently introduced. Such devices are ideally suited for many application domains ranging from multimedia to communication. A major challenge to their wider use is the lack of high level programming and design space exploration tools. This tutorial focuses on three aspects of this emerging technology: (1) the intrinsic potential of the temporal/spatial paradigm (2) The wide range of architectures, fine and coarse grained, and the trade-offs between performance and flexibility. (3) A survey of current and future applications in multimedia and mobile communication and analysis of their performance and energy requirements. It is intended for an audience of developers and researchers in high-end embedded systems. The tutorial presents methods for reliable system design. We consider systems realised on a single chip, systems consisting of several integrated components (possibly components off-the shelf-COTS), and distributed systems. We address both hardware (computation and communication) and software aspects of reliable system design. This tutorial is intended for researchers in EDA, system/chip designers and software developers for integrated systems, as well as for managers who want to learn about reliable design and how this area evolved in view of the current technology trends. The tutorial covers a spectrum of diagnosis and debug topics from the basic concepts to future challenges, over the life-cycle of a product. Established diagnosis procedures fault dictionaries, post-test fault simulation, and hardware-based backtracking will be discussed, followed by recent enhancements and advanced diagnosis topics, including methods for locating defects, approximation techniques for identifying unmodelled faults, deductive analysis, Iddq-based diagnosis, diagnosis for delay-faults, scan-chain diagnosis, BIST-based diagnosis, and design-for-diagnosability techniques. The tutorial then will focus on silicon debug techniques, design-for-debug techniques, and applications to yield improvement. Successful diagnosis methods used in real industrial products, industrial experiences, and case studies will be presented in this tutorial. determined to find out where those puzzling …
{"title":"The coming of age of reconfigurable computing-potentials and challenges of a new technology [Tutorial]","authors":"W. Najjar, F. Kurdahi, K. Vissers","doi":"10.1109/DATE.2004.1268810","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268810","url":null,"abstract":"Addresses modelling for analysis and optimisation of MPSoC architectures including hardware and software layers such as drivers, run-time systems and application APIs. Different scheduling strategies, communication behaviours and performance requirements must be matched and combined on a single system. 4. Presents the DELI experience to show that application level software development can be overlapped with the development of the rest of the system. DELI is aimed to generating portable HdS taking into account real-time constraints and low-level interactions with OS and the HW during early prototyping. Platforms that combine CPUs with a reconfigurable fabric on the same chip have been recently introduced. Such devices are ideally suited for many application domains ranging from multimedia to communication. A major challenge to their wider use is the lack of high level programming and design space exploration tools. This tutorial focuses on three aspects of this emerging technology: (1) the intrinsic potential of the temporal/spatial paradigm (2) The wide range of architectures, fine and coarse grained, and the trade-offs between performance and flexibility. (3) A survey of current and future applications in multimedia and mobile communication and analysis of their performance and energy requirements. It is intended for an audience of developers and researchers in high-end embedded systems. The tutorial presents methods for reliable system design. We consider systems realised on a single chip, systems consisting of several integrated components (possibly components off-the shelf-COTS), and distributed systems. We address both hardware (computation and communication) and software aspects of reliable system design. This tutorial is intended for researchers in EDA, system/chip designers and software developers for integrated systems, as well as for managers who want to learn about reliable design and how this area evolved in view of the current technology trends. The tutorial covers a spectrum of diagnosis and debug topics from the basic concepts to future challenges, over the life-cycle of a product. Established diagnosis procedures fault dictionaries, post-test fault simulation, and hardware-based backtracking will be discussed, followed by recent enhancements and advanced diagnosis topics, including methods for locating defects, approximation techniques for identifying unmodelled faults, deductive analysis, Iddq-based diagnosis, diagnosis for delay-faults, scan-chain diagnosis, BIST-based diagnosis, and design-for-diagnosability techniques. The tutorial then will focus on silicon debug techniques, design-for-debug techniques, and applications to yield improvement. Successful diagnosis methods used in real industrial products, industrial experiences, and case studies will be presented in this tutorial. determined to find out where those puzzling …","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122437882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268811
G. De Micheli, R. Iyer
Addresses modelling for analysis and optimisation of MPSoC architectures including hardware and software layers such as drivers, run-time systems and application APIs. Different scheduling strategies, communication behaviours and performance requirements must be matched and combined on a single system. 4. Presents the DELI experience to show that application level software development can be overlapped with the development of the rest of the system. DELI is aimed to generating portable HdS taking into account real-time constraints and low-level interactions with OS and the HW during early prototyping. Platforms that combine CPUs with a reconfigurable fabric on the same chip have been recently introduced. Such devices are ideally suited for many application domains ranging from multimedia to communication. A major challenge to their wider use is the lack of high level programming and design space exploration tools. This tutorial focuses on three aspects of this emerging technology: (1) the intrinsic potential of the temporal/spatial paradigm (2) The wide range of architectures, fine and coarse grained, and the trade-offs between performance and flexibility. (3) A survey of current and future applications in multimedia and mobile communication and analysis of their performance and energy requirements. It is intended for an audience of developers and researchers in high-end embedded systems. The tutorial presents methods for reliable system design. We consider systems realised on a single chip, systems consisting of several integrated components (possibly components off-the shelf-COTS), and distributed systems. We address both hardware (computation and communication) and software aspects of reliable system design. This tutorial is intended for researchers in EDA, system/chip designers and software developers for integrated systems, as well as for managers who want to learn about reliable design and how this area evolved in view of the current technology trends. The tutorial covers a spectrum of diagnosis and debug topics from the basic concepts to future challenges, over the life-cycle of a product. Established diagnosis procedures fault dictionaries, post-test fault simulation, and hardware-based backtracking will be discussed, followed by recent enhancements and advanced diagnosis topics, including methods for locating defects, approximation techniques for identifying unmodelled faults, deductive analysis, Iddq-based diagnosis, diagnosis for delay-faults, scan-chain diagnosis, BIST-based diagnosis, and design-for-diagnosability techniques. The tutorial then will focus on silicon debug techniques, design-for-debug techniques, and applications to yield improvement. Successful diagnosis methods used in real industrial products, industrial experiences, and case studies will be presented in this tutorial. determined to find out where those puzzling …
{"title":"Reliable design: a system perspective [Tutorial]","authors":"G. De Micheli, R. Iyer","doi":"10.1109/DATE.2004.1268811","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268811","url":null,"abstract":"Addresses modelling for analysis and optimisation of MPSoC architectures including hardware and software layers such as drivers, run-time systems and application APIs. Different scheduling strategies, communication behaviours and performance requirements must be matched and combined on a single system. 4. Presents the DELI experience to show that application level software development can be overlapped with the development of the rest of the system. DELI is aimed to generating portable HdS taking into account real-time constraints and low-level interactions with OS and the HW during early prototyping. Platforms that combine CPUs with a reconfigurable fabric on the same chip have been recently introduced. Such devices are ideally suited for many application domains ranging from multimedia to communication. A major challenge to their wider use is the lack of high level programming and design space exploration tools. This tutorial focuses on three aspects of this emerging technology: (1) the intrinsic potential of the temporal/spatial paradigm (2) The wide range of architectures, fine and coarse grained, and the trade-offs between performance and flexibility. (3) A survey of current and future applications in multimedia and mobile communication and analysis of their performance and energy requirements. It is intended for an audience of developers and researchers in high-end embedded systems. The tutorial presents methods for reliable system design. We consider systems realised on a single chip, systems consisting of several integrated components (possibly components off-the shelf-COTS), and distributed systems. We address both hardware (computation and communication) and software aspects of reliable system design. This tutorial is intended for researchers in EDA, system/chip designers and software developers for integrated systems, as well as for managers who want to learn about reliable design and how this area evolved in view of the current technology trends. The tutorial covers a spectrum of diagnosis and debug topics from the basic concepts to future challenges, over the life-cycle of a product. Established diagnosis procedures fault dictionaries, post-test fault simulation, and hardware-based backtracking will be discussed, followed by recent enhancements and advanced diagnosis topics, including methods for locating defects, approximation techniques for identifying unmodelled faults, deductive analysis, Iddq-based diagnosis, diagnosis for delay-faults, scan-chain diagnosis, BIST-based diagnosis, and design-for-diagnosability techniques. The tutorial then will focus on silicon debug techniques, design-for-debug techniques, and applications to yield improvement. Successful diagnosis methods used in real industrial products, industrial experiences, and case studies will be presented in this tutorial. determined to find out where those puzzling …","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116297663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268809
A. Jerraya, F. Pospiech, R. Ernst, G. Desoli
The tutorial presents an introduction into “DfY/DfM Design for Yield and Manufacturability” covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment.
{"title":"Programming models for multiprocessor SoC (full-day) [Tutorial]","authors":"A. Jerraya, F. Pospiech, R. Ernst, G. Desoli","doi":"10.1109/DATE.2004.1268809","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268809","url":null,"abstract":"The tutorial presents an introduction into “DfY/DfM Design for Yield and Manufacturability” covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268814
D. Harris, T. Grutkowski
{"title":"Advanced domino circuit design [Tutorial]","authors":"D. Harris, T. Grutkowski","doi":"10.1109/DATE.2004.1268814","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268814","url":null,"abstract":"","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129209836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1269245
T. Schubert, J. Hanisch, J. Gerlach, Appell J-E, W. Nebel
This paper describes the experiences and results that were made with a systemC-based design flow for the implementation of an automotive digital hardware design. We present the refinement process starting from an initial high-level executable specification in C++ via systemC down to a gate-level description. We compare the synthesis results of the systemC-based system-level design flow with those from a traditional VHDL-based register-transfer level design flow in terms of efficiency and simulation performance.
{"title":"Evaluation of a refinement-driven systemC/spl trade/-based design flow","authors":"T. Schubert, J. Hanisch, J. Gerlach, Appell J-E, W. Nebel","doi":"10.1109/DATE.2004.1269245","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269245","url":null,"abstract":"This paper describes the experiences and results that were made with a systemC-based design flow for the implementation of an automotive digital hardware design. We present the refinement process starting from an initial high-level executable specification in C++ via systemC down to a gate-level description. We compare the synthesis results of the systemC-based system-level design flow with those from a traditional VHDL-based register-transfer level design flow in terms of efficiency and simulation performance.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116299324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268813
C. Hecker, D. Amos
ISSP (Instant Solution Silicon Platform), the leading Structured ASIC Technology, was of great interest when introduced by NEC Electronics at DATE 2003. Now this tutorial will give you all the essential information required to judge the competitive advantage that using Structured ASIC can give you in your next project. ISSP devices are mask-programmed to your specification with very low NRE costs and short lead time. The Design is implemented through the optimised and dedicated synthesis technology of Synplicity's Synplify ASIC tool. This tutorial shows how you can use either your ASIC or FPGA expertise to use ISSP without excessive tool costs or massive retraining. Despite rumours of their demise, domino circuits are still indispensable in the design of high speed CMOS chips because they offer a 1.5-2x performance advantage over static logic. This tutorial briefly reviews basic dominio design issues, then compares and contrasts a wide variety of high-performance domino and nonmonotonic dynamic sequencing techniques. It then details the domino methodology used on the Itanium 2 microprocessors and explores pitfalls discovered during silicon debug. This tutorial is intended for circuit, logic, CAD, and test engineers interested in high-performance domino design.
{"title":"Stuctured ASIC tutorial: essential information on devices and design flow (industrial tutorial)","authors":"C. Hecker, D. Amos","doi":"10.1109/DATE.2004.1268813","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268813","url":null,"abstract":"ISSP (Instant Solution Silicon Platform), the leading Structured ASIC Technology, was of great interest when introduced by NEC Electronics at DATE 2003. Now this tutorial will give you all the essential information required to judge the competitive advantage that using Structured ASIC can give you in your next project. ISSP devices are mask-programmed to your specification with very low NRE costs and short lead time. The Design is implemented through the optimised and dedicated synthesis technology of Synplicity's Synplify ASIC tool. This tutorial shows how you can use either your ASIC or FPGA expertise to use ISSP without excessive tool costs or massive retraining. Despite rumours of their demise, domino circuits are still indispensable in the design of high speed CMOS chips because they offer a 1.5-2x performance advantage over static logic. This tutorial briefly reviews basic dominio design issues, then compares and contrasts a wide variety of high-performance domino and nonmonotonic dynamic sequencing techniques. It then details the domino methodology used on the Itanium 2 microprocessors and explores pitfalls discovered during silicon debug. This tutorial is intended for circuit, logic, CAD, and test engineers interested in high-performance domino design.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126673571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268806
D. Gizopoulos, G. Eide, A. Crouch, K. Posse
This tutorial addresses state-of-the-art methods used to verify properties of sequential digital systems. The focus is on providing an overview of the main technologies and their applicability to complex designs. We cover the core algorithms involved in model checking, symbolic simulation and theorem proving methods, their application for specific aspects of formal verification and their deployment in verification software currently available both from industry and from academia.
{"title":"DF for low cost testers [Tutorial]","authors":"D. Gizopoulos, G. Eide, A. Crouch, K. Posse","doi":"10.1109/DATE.2004.1268806","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268806","url":null,"abstract":"This tutorial addresses state-of-the-art methods used to verify properties of sequential digital systems. The focus is on providing an overview of the main technologies and their applicability to complex designs. We cover the core algorithms involved in model checking, symbolic simulation and theorem proving methods, their application for specific aspects of formal verification and their deployment in verification software currently available both from industry and from academia.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132647569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268824
J. Baumgartner, A. Kuehlmann
Bounded model checking (BMC) has gained widespread industrial use due to its relative scalability. Its exhaustiveness over all valid input vectors allows it to expose arbitrarily complex design flaws. However, BMC is limited to analyzing only a specific time window, hence will only expose those flaws which manifest within that window and thus connect readily prove correctness. The diameter of a design has thus become an important concept - a bounded check of depth equal to the diameter constitutes a complete proof. While the diameter of a design may be exponential in the number of its state elements, in practice it often ranges from tens to a few hundred regardless of design size. Therefore, a powerful diameter overapproximation technique may enable automatic proofs that otherwise would be infeasible. Unfortunately, exact diameter calculation requires exponential resources, and overapproximation techniques may yield exponentially loose bounds. In this paper, we provide a general approach for enabling the use of structural transformations, such as redundancy removal, retiming, and target enlargement, to tighten the bounds obtained by arbitrary diameter approximation techniques. Numerous experiments demonstrate that this approach may significantly increase the set of designs for which practically useful diameter bounds may be obtained.
{"title":"Enhanced diameter bounding via structural transformation","authors":"J. Baumgartner, A. Kuehlmann","doi":"10.1109/DATE.2004.1268824","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268824","url":null,"abstract":"Bounded model checking (BMC) has gained widespread industrial use due to its relative scalability. Its exhaustiveness over all valid input vectors allows it to expose arbitrarily complex design flaws. However, BMC is limited to analyzing only a specific time window, hence will only expose those flaws which manifest within that window and thus connect readily prove correctness. The diameter of a design has thus become an important concept - a bounded check of depth equal to the diameter constitutes a complete proof. While the diameter of a design may be exponential in the number of its state elements, in practice it often ranges from tens to a few hundred regardless of design size. Therefore, a powerful diameter overapproximation technique may enable automatic proofs that otherwise would be infeasible. Unfortunately, exact diameter calculation requires exponential resources, and overapproximation techniques may yield exponentially loose bounds. In this paper, we provide a general approach for enabling the use of structural transformations, such as redundancy removal, retiming, and target enlargement, to tighten the bounds obtained by arbitrary diameter approximation techniques. Numerous experiments demonstrate that this approach may significantly increase the set of designs for which practically useful diameter bounds may be obtained.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134547393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268817
M. Speitel, B. Niemann, A. Braun, K. Einwich, C. Haubelt, F. Mayer
Summary form only given, as follows. Even with new design languages coming up, SystemC is widely accepted by EDA companies and used in many design teams. The tutorial gives an extensive overview of the application of SystemC for various aspects of system-on-chip design. It starts with an introduction to SystemC 2.0. Modelling at different levels of abstraction - from system development down to a synthesisable ASIC implementation - are covered. The tutorial is extended by HW/SW partitioning methodologies using SystemC, and includes analogue and mixed analogue/digital modelling with SystemC AMS. The verification of hardware dependent software and the novel SystemC verification library and its usage are also presented. Intended audience: This master course is targeted to designers, who want to acquire basic knowledge of SystemC and its applications as well as design managers, searching for an inside view on the usage of SystemC in a C/C++ based design flow.
{"title":"Modern design techniques with systemC [Tutorial]","authors":"M. Speitel, B. Niemann, A. Braun, K. Einwich, C. Haubelt, F. Mayer","doi":"10.1109/DATE.2004.1268817","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268817","url":null,"abstract":"Summary form only given, as follows. Even with new design languages coming up, SystemC is widely accepted by EDA companies and used in many design teams. The tutorial gives an extensive overview of the application of SystemC for various aspects of system-on-chip design. It starts with an introduction to SystemC 2.0. Modelling at different levels of abstraction - from system development down to a synthesisable ASIC implementation - are covered. The tutorial is extended by HW/SW partitioning methodologies using SystemC, and includes analogue and mixed analogue/digital modelling with SystemC AMS. The verification of hardware dependent software and the novel SystemC verification library and its usage are also presented. Intended audience: This master course is targeted to designers, who want to acquire basic knowledge of SystemC and its applications as well as design managers, searching for an inside view on the usage of SystemC in a C/C++ based design flow.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126583607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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