A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993084
M. Ohashi, T. Hashimoto, S. Kuromaru, M. Matsuo, T. Mori-iwa, M. Hamada, Y. Sugisawa, M. Arita, H. Tomita, M. Hoshino, H. Miyajima, T. Nakamura, K. Ishida, T. Kimura, Y. Kohashi, T. Kondo, A. Inoue, H. Fujimoto, K. Watada, T. Fukunaga, T. Nishi, H. Ito, J. Michiyama
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引用次数: 22

Abstract

A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.
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用于移动应用的27 MHz 11.1 mW MPEG-4视频解码器LSI
集成了896 kb嵌入式SRAM帧缓冲器和嵌入式视频显示引擎的单片MPEG-4视频解码器LSI在27 MHz工作时消耗11.1 mW。该芯片采用0.18 μm 1.5 V四金属CMOS技术，在37.26 mm/sup 2/芯片上实现QCIF 15 Hz H.263和Simple@L1解码能力。
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
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