Routing Congestion Aware Cell Library Development for Monolithic 3D ICs

Abstract

According to International Roadmap for Devices and Systems (IRDS), after 2024, there is no headroom for 2D geometry scaling. By 2024, IRDS predicts that monolithic 3D integration technology will be one of the most critical performance boosters. This prediction follows the highly promising and relatively recent improvements on the fabrication of second-tier devices on a single substrate. In this study, a fully functional and open source cell library is developed to design and characterize large-scale monolithic 3D ICs. The second version of the 3D cell library is equipped with the required files for integration into existing design automation tools, thereby enabling chip-level benchmarking. Furthermore, multiple versions of the library are proposed to investigate the tradeoffs among routability, timing, power, and area characteristics. The 3D library can also be used to analyze some of the important issues in monolithic 3D ICs, such as chip-level thermal characteristics, efficacy of various thermal management methodologies, and design-for-test methods for monolithic 3D integration.