ESD implantations in 0.18-/spl mu/m salicided CMOS technology for on-chip ESD protection with layout consideration

M. Ker, Che-Hao Chuang
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引用次数: 23

Abstract

ESD robustness of CMOS devices used in the I/O pad is a major reliability issue as the diffusion junction depth is reduced and LDD (lightly-doped drain)/salicide structures are generally used in sub-quarter-micron CMOS technology. In order to enhance ESD robustness, some ESD implantations have been reported for inclusion into the process flow to modify the device structures for ESD protection (Lee, 1997; Hsue and Ko, 1994; Lowrey and Chance, 1996; Yang, 2000). In this paper, the effectiveness of different ESD implantation solutions on NMOS and diode devices for ESD protection is investigated in a 0.18 /spl mu/m salicided bulk CMOS process. The second breakdown current (It2) of the fabricated devices is measured by the transmission line pulse generator (TLPG). The human-body-model (HBM) and the machine-model (MM) ESD levels of these devices are also measured and compared. The layout dependence of NMOS devices and diodes with different ESD implantations are also investigated.
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ESD植入在0.18-/spl mu/m的盐化CMOS技术中进行片上ESD保护,并考虑布局
随着扩散结深度的降低和LDD(轻掺杂漏极)/盐化物结构通常用于亚四分之一微米CMOS技术,用于I/O焊片的CMOS器件的ESD稳稳性是一个主要的可靠性问题。为了增强ESD的稳健性,一些ESD植入物已经被报道纳入到工艺流程中,以修改ESD保护的器件结构(Lee, 1997;Hsue and Ko, 1994;Lowrey and Chance, 1996;杨,2000)。本文在0.18 /spl mu/m的盐化体CMOS工艺中,研究了不同的ESD注入溶液对NMOS和二极管器件的ESD保护效果。利用传输线脉冲发生器(TLPG)测量器件的二次击穿电流(It2)。测量并比较了这些器件的人体模型(HBM)和机器模型(MM) ESD水平。研究了不同ESD植入方式对NMOS器件和二极管布局的影响。
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