Pub Date : 2001-07-13DOI: 10.1109/IPFA.2001.941488
C. Burmer, P. Egger
Automatic test pattern generation (ATPG) is recommended in order to obtain high test coverage quickly. For failure analysis, some standard ATPG tools offer in addition a feature to perform fault diagnosis on full scan designs. Software fault localization techniques become increasingly important in future designs, since in highly complex VHDL programmed designs, a standard analysis using functional test vectors is expendable and time consuming. This paper describes all steps necessary for project set-up and a flow for fault diagnosis. In order to minimize the list of possible failures (given by the tool) and to determine the physical location of the defect (x,y,z), a failure localization flow is presented. Initial results on ICs with both failures purposely induced by focused ion beam and real production failures represents an excellent starting point for further fault localization.
{"title":"Software aided failure analysis using ATPG tool","authors":"C. Burmer, P. Egger","doi":"10.1109/IPFA.2001.941488","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941488","url":null,"abstract":"Automatic test pattern generation (ATPG) is recommended in order to obtain high test coverage quickly. For failure analysis, some standard ATPG tools offer in addition a feature to perform fault diagnosis on full scan designs. Software fault localization techniques become increasingly important in future designs, since in highly complex VHDL programmed designs, a standard analysis using functional test vectors is expendable and time consuming. This paper describes all steps necessary for project set-up and a flow for fault diagnosis. In order to minimize the list of possible failures (given by the tool) and to determine the physical location of the defect (x,y,z), a failure localization flow is presented. Initial results on ICs with both failures purposely induced by focused ion beam and real production failures represents an excellent starting point for further fault localization.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121908078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-13DOI: 10.1109/IPFA.2001.941452
J. Chin, M. Palaniappan, J. Phang, D. Chan, C. E. Soh, G. Gilfeather
The single contact optical beam induced currents (SCOBIC) method is a new failure analysis technique. By connecting the substrate or power pins of an integrated circuit to the current amplifier, many junctions can be imaged. This is in contrast to the optical beam induced current (OBIC) technique, where only the junction directly connected to the current amplifier is imaged. The implementation of the SCOBIC approach is discussed and experimental results which validate the SCOBIC technique are presented. Application of the SCOBIC technique for CMOS front side and back side devices is also discussed.
{"title":"Single contact optical beam induced currents (SCOBIC)-technique and applications","authors":"J. Chin, M. Palaniappan, J. Phang, D. Chan, C. E. Soh, G. Gilfeather","doi":"10.1109/IPFA.2001.941452","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941452","url":null,"abstract":"The single contact optical beam induced currents (SCOBIC) method is a new failure analysis technique. By connecting the substrate or power pins of an integrated circuit to the current amplifier, many junctions can be imaged. This is in contrast to the optical beam induced current (OBIC) technique, where only the junction directly connected to the current amplifier is imaged. The implementation of the SCOBIC approach is discussed and experimental results which validate the SCOBIC technique are presented. Application of the SCOBIC technique for CMOS front side and back side devices is also discussed.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132381498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-13DOI: 10.1109/IPFA.2001.941465
G. Ang, Y. Hua, S. K. Loh, Yogaspari, S. Redkar
A case of the application of passive voltage contrast (PVC) and focused ion beam (FIB) to failure analysis of metal interconnection or via defects in wafer fabrication was studied. We have proposed a simple, efficient and cost-saving identification method of locating the 1st, 2nd, 3rd and higher defective vias in the via chain through FIB-induced PVC and its precise cross-sectioning. Such a technique proves useful as it enables us to understand whether all the defective vias in the via chain exhibit the same failure phenomenon or display any particular failure pattern which will help the failure analysis or process engineers to determine the failure mechanism.
{"title":"Application of passive voltage contrast and focused ion beam on failure analysis of metal via defect in wafer fabrication","authors":"G. Ang, Y. Hua, S. K. Loh, Yogaspari, S. Redkar","doi":"10.1109/IPFA.2001.941465","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941465","url":null,"abstract":"A case of the application of passive voltage contrast (PVC) and focused ion beam (FIB) to failure analysis of metal interconnection or via defects in wafer fabrication was studied. We have proposed a simple, efficient and cost-saving identification method of locating the 1st, 2nd, 3rd and higher defective vias in the via chain through FIB-induced PVC and its precise cross-sectioning. Such a technique proves useful as it enables us to understand whether all the defective vias in the via chain exhibit the same failure phenomenon or display any particular failure pattern which will help the failure analysis or process engineers to determine the failure mechanism.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123516641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-13DOI: 10.1109/IPFA.2001.941495
N. Stojadinovic, S. Djoric-Veljkovic, I. Manic, V. Davidovic, S. Golubovic
The effects of pre-irradiation elevated-temperature bias stressing on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift in stressed devices and considerable mobility reduction in unstressed devices have been observed. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects.
{"title":"Effects of elevated-temperature bias stressing on radiation response in power VDMOSFETs","authors":"N. Stojadinovic, S. Djoric-Veljkovic, I. Manic, V. Davidovic, S. Golubovic","doi":"10.1109/IPFA.2001.941495","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941495","url":null,"abstract":"The effects of pre-irradiation elevated-temperature bias stressing on radiation response of power VDMOSFETs have been investigated. Larger irradiation induced threshold voltage shift in stressed devices and considerable mobility reduction in unstressed devices have been observed. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129103085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941470
J. Y. Dai, S. Ansari, C. L. Tay, S. F. Tee, E. Er, S. Redkar
In advanced CMOS manufacturing, when aspects including contacts with W plugs are being miniaturised, high resistance contacts causing low yield becomes a common issue. In failure analysis, contact failures such due to insufficient trench etching and particle blocking which can cause extremely high resistance or opens are relatively easy to isolate and identify. However, for those contacts with resistance marginally higher than normal, the root cause is very difficult to identify by traditional methods like passive voltage contrast (PVC) and scanning electron microscopy (SEM), or focused ion beam (FIB) technology, which is quite successful for the open contact cases. This contact resistance variation is normally due to the narrow process window or process parameters drifting and may lead to relatively low yield. Direct observation of these contacts by transmission electron microscopy (TEM) provides detailed microstructural and chemical information which correlates to the failure and are unobtainable by other material analysis techniques. In this paper, we report a novel failure mechanism of the high resistance contact revealed by TEM study. Direct evidence is provided to show the impact of process changes on the contact structure which may correlate to the high resistance.
{"title":"Failure mechanism study for high resistance contact in CMOS devices","authors":"J. Y. Dai, S. Ansari, C. L. Tay, S. F. Tee, E. Er, S. Redkar","doi":"10.1109/IPFA.2001.941470","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941470","url":null,"abstract":"In advanced CMOS manufacturing, when aspects including contacts with W plugs are being miniaturised, high resistance contacts causing low yield becomes a common issue. In failure analysis, contact failures such due to insufficient trench etching and particle blocking which can cause extremely high resistance or opens are relatively easy to isolate and identify. However, for those contacts with resistance marginally higher than normal, the root cause is very difficult to identify by traditional methods like passive voltage contrast (PVC) and scanning electron microscopy (SEM), or focused ion beam (FIB) technology, which is quite successful for the open contact cases. This contact resistance variation is normally due to the narrow process window or process parameters drifting and may lead to relatively low yield. Direct observation of these contacts by transmission electron microscopy (TEM) provides detailed microstructural and chemical information which correlates to the failure and are unobtainable by other material analysis techniques. In this paper, we report a novel failure mechanism of the high resistance contact revealed by TEM study. Direct evidence is provided to show the impact of process changes on the contact structure which may correlate to the high resistance.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124982000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941477
W. McMahon, A. Haggag, K. Hess
As CMOS technology scales down to the regime where atomic size becomes significant, it has become increasingly important to take a physics-of-failure approach to device design by understanding the underlying mechanisms of MOSFET degradation. We give a model which describes the time dependence of degradation of a general class of failure modes, applying the model specifically to hot-electron interface-state generation. With several typical measurements of device degradation characteristics, this model can be used to derive the failure function and extract the Weibull parameter for failure modes in this class.
{"title":"Modeling failure modes for submicron devices","authors":"W. McMahon, A. Haggag, K. Hess","doi":"10.1109/IPFA.2001.941477","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941477","url":null,"abstract":"As CMOS technology scales down to the regime where atomic size becomes significant, it has become increasingly important to take a physics-of-failure approach to device design by understanding the underlying mechanisms of MOSFET degradation. We give a model which describes the time dependence of degradation of a general class of failure modes, applying the model specifically to hot-electron interface-state generation. With several typical measurements of device degradation characteristics, this model can be used to derive the failure function and extract the Weibull parameter for failure modes in this class.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121869836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941497
M. Dunga, A. Kumar, V. Ramgopal Rao
In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations.
本文采用一种新型的栅极感应漏极电流(GIDL)技术，对横向不对称沟道(LAC)和传统均匀掺杂沟道(均匀)SOI mosfet中的浮体效应进行了分析。利用GIDL电流技术对LAC和均匀SOI mosfet的寄生双极电流增益/spl beta/进行了实验测量。利用二维器件模拟解释了在LAC SOI mosfet中观察到的较低寄生双极电流增益。
{"title":"Analysis of floating body effects in thin film SOI MOSFETs using the GIDL current technique","authors":"M. Dunga, A. Kumar, V. Ramgopal Rao","doi":"10.1109/IPFA.2001.941497","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941497","url":null,"abstract":"In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941471
Zhang Wan-rong, Li Zhi-guo, Mu Fu-chen, Wang Li-xin, Sun Ying-hua, Cheng Yao-hai, Chen Jian-xin, Shen Guang-di
A rapid evaluation method, the temperature ramp method, for GaAs MESFET ohmic contacts is proposed. By use of this method, activation energy for ohmic contact degradation can be obtained using less time and a smaller number of samples than traditional methods, and the results are in agreement with those obtained by traditional methods. In accordance with some drawbacks of traditional AuGeNi-Au ohmic contacts, a new ohmic contacts system with TiN diffusion barrier layer is proposed. Experimental results show that the reliability of ohmic contacts with TiN is greatly superior to that of traditional AuGeNi-Au ohmic contacts.
{"title":"A rapid evaluation method for degradation activation energy of n-GaAs ohmic contacts with and without TiN diffusion barrier layers","authors":"Zhang Wan-rong, Li Zhi-guo, Mu Fu-chen, Wang Li-xin, Sun Ying-hua, Cheng Yao-hai, Chen Jian-xin, Shen Guang-di","doi":"10.1109/IPFA.2001.941471","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941471","url":null,"abstract":"A rapid evaluation method, the temperature ramp method, for GaAs MESFET ohmic contacts is proposed. By use of this method, activation energy for ohmic contact degradation can be obtained using less time and a smaller number of samples than traditional methods, and the results are in agreement with those obtained by traditional methods. In accordance with some drawbacks of traditional AuGeNi-Au ohmic contacts, a new ohmic contacts system with TiN diffusion barrier layer is proposed. Experimental results show that the reliability of ohmic contacts with TiN is greatly superior to that of traditional AuGeNi-Au ohmic contacts.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129574308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941498
A. Khamesra, R. Lal, J. Vasi, K. P. Kumar, J. Sin
There has been increasing interest in polysilicon thin film transistors (TFTs) for high-performance applications, particularly in high-resolution displays. For these applications, the primary requirement is that the TFTs have a low threshold voltage, low and stable leakage current and reasonably high carrier mobility. The poly-Si TFTs typically have sufficiently large mobilities to be used for high-drive and moderately high-frequency applications. However, since low temperatures are used in poly-Si TFT fabrication, both semiconducting and insulating layers are of poorer quality than those used in crystalline-Si technology. Consequently, long term TFT stability is an important issue. A considerable amount of research has focused on the stability of poly-Si TFTs. The instabilities are basically associated with hot carrier injection and degradation, negative gate bias instability and gate-induced carrier injection and trapping (Young, 1996). This leads to degradation of several device parameters such as threshold voltage, mobility, transconductance, and subthreshold slope. The work presented here is a comprehensive study of degradation in low temperature (/spl les/600/spl deg/C) poly-Si TFTs due to high-field, hot-carrier and ionizing radiation stressing. This unified approach makes it possible to identify the key reasons for degradation. Furthermore, a systematic study of the dependence on device geometry, as reported here, also helps understanding of the degradation mechanisms.
{"title":"Device degradation of n-channel poly-Si TFTs due to high-field, hot-carrier and radiation stressing","authors":"A. Khamesra, R. Lal, J. Vasi, K. P. Kumar, J. Sin","doi":"10.1109/IPFA.2001.941498","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941498","url":null,"abstract":"There has been increasing interest in polysilicon thin film transistors (TFTs) for high-performance applications, particularly in high-resolution displays. For these applications, the primary requirement is that the TFTs have a low threshold voltage, low and stable leakage current and reasonably high carrier mobility. The poly-Si TFTs typically have sufficiently large mobilities to be used for high-drive and moderately high-frequency applications. However, since low temperatures are used in poly-Si TFT fabrication, both semiconducting and insulating layers are of poorer quality than those used in crystalline-Si technology. Consequently, long term TFT stability is an important issue. A considerable amount of research has focused on the stability of poly-Si TFTs. The instabilities are basically associated with hot carrier injection and degradation, negative gate bias instability and gate-induced carrier injection and trapping (Young, 1996). This leads to degradation of several device parameters such as threshold voltage, mobility, transconductance, and subthreshold slope. The work presented here is a comprehensive study of degradation in low temperature (/spl les/600/spl deg/C) poly-Si TFTs due to high-field, hot-carrier and ionizing radiation stressing. This unified approach makes it possible to identify the key reasons for degradation. Furthermore, a systematic study of the dependence on device geometry, as reported here, also helps understanding of the degradation mechanisms.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126886947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-07-09DOI: 10.1109/IPFA.2001.941469
A. Siritaratiwat, N. Suwannata, J. Pinnoi, C. Puprichitkun
The electrostatic discharge (ESD) effect is widely known as a main cause of damage in giant magnetoresistance (GMR) heads (Wallash and Kim, 1995). The transient current may strike the GMR head directly by passing the leads (Li-Yan Zhu, 1999) and this may be prevented by shunting the GMR leads (Bajorek et al, 1995). However, after completing the head gimbal assembly (HGA) production, the shunt leads have to be trimmed in order to test its electrical characteristics. This is thought to cause the ESD effect while trimming the shunt tab of a GMR head, and is investigated here.
{"title":"ESD effect in GMR heads in the trim shunt tab process","authors":"A. Siritaratiwat, N. Suwannata, J. Pinnoi, C. Puprichitkun","doi":"10.1109/IPFA.2001.941469","DOIUrl":"https://doi.org/10.1109/IPFA.2001.941469","url":null,"abstract":"The electrostatic discharge (ESD) effect is widely known as a main cause of damage in giant magnetoresistance (GMR) heads (Wallash and Kim, 1995). The transient current may strike the GMR head directly by passing the leads (Li-Yan Zhu, 1999) and this may be prevented by shunting the GMR leads (Bajorek et al, 1995). However, after completing the head gimbal assembly (HGA) production, the shunt leads have to be trimmed in order to test its electrical characteristics. This is thought to cause the ESD effect while trimming the shunt tab of a GMR head, and is investigated here.","PeriodicalId":297053,"journal":{"name":"Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548)","volume":"2001 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132427758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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