{"title":"An approach to multi-paradigm controller synthesis from timing diagram specifications","authors":"Wolf-Dieter Tiedemann","doi":"10.1109/EURDAC.1992.246314","DOIUrl":null,"url":null,"abstract":"The author reports on two high-level synthesis methods to derive controller implementations following different design paradigms from a common natural specification by timing diagrams. The first method automatically generates a Mealy automaton to be an input for a variety of excellent finite state machine (FSM) design algorithms. The second method supports an interactive bottom-up synthesis of asynchronous designs. Both methods are founded on the same mathematical basis, notably a process calculus. Due to their formal manifestation, every transformation (synthesis step) is verifiable. This leads to guaranteed correct implementations.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246314","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
The author reports on two high-level synthesis methods to derive controller implementations following different design paradigms from a common natural specification by timing diagrams. The first method automatically generates a Mealy automaton to be an input for a variety of excellent finite state machine (FSM) design algorithms. The second method supports an interactive bottom-up synthesis of asynchronous designs. Both methods are founded on the same mathematical basis, notably a process calculus. Due to their formal manifestation, every transformation (synthesis step) is verifiable. This leads to guaranteed correct implementations.<>