Analysis and optimization of IIP2 in CMOS direct down-converters

D. Manstretta, F. Svelto
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引用次数: 22

Abstract

Two mechanisms are responsible for second order intermodulation in CMOS down-converters: RF self-mixing and device non-linearity and mismatches. An intuitive model and analytical expressions are provided for both of them. A down-converter prototype, drawing 3.2 mA from a 1.8 V supply, part of a fully integrated 0.18 /spl mu/m CMOS UMTS receiver front-end shows 66 dBm IIP2 and 16 dBm IIP3.
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CMOS直接下变频器中IIP2的分析与优化
两种机制负责二阶互调在CMOS下变频器:射频自混频和器件非线性和不匹配。给出了直观的模型和解析表达式。下变频器原型,从1.8 V电源汲取3.2 mA,完全集成的0.18 /spl mu/m CMOS UMTS接收器前端的一部分显示66 dBm IIP2和16 dBm IIP3。
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