Automatic Verification Plan Generation to Speed up SoC Verification

Abstract

In this work developed in the SIMBA project, we present a novel methodology to reduce the time for System-on-Chip (SoC) verification significantly by automatically generating a verification plan from the specification document. We consider the specification as a series of semi-formal textual use cases, which is a widely accepted document-based hardware specification format and suitable for automatic post-processing. We use an RFID SoC to demonstrate the benefits of our methodology. We show that it significantly reduces the time for functional verification, removes errors in the specification and detects a number of discrepancies between the RFID SoC and the RFID protocol specification.