Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738279
P. Yliuntinen, S. Virtanen
SystemC has evolved from a limited simulation library towards an extensive system design framework since its introduction almost 10 years ago. Currently it is one of the most widely used system design languages and is supported by major EDA vendors. The cost for developing SystemC into a stable and widely adopted system design framework has in our experience been the inherent need of rewriting complex and well-modularized system models with every new SystemC release. In this paper we present our experiences in continuous development of a system level processor model through SystemC version upgrades. The focus is on our latest transition from SystemC 1.1 to version 2.2. In our practical experience, transitions from an older version of SystemC to a newer one have always required rewriting significant amounts, if not most, of the model code. We also experimented with synthesis after the upgrade, and concluded that the synthesis capabilities of SystemC for complex object oriented models are still severely limited at best.
{"title":"Survival of an object oriented simulation framework through SystemC version upgrades","authors":"P. Yliuntinen, S. Virtanen","doi":"10.1109/NORCHP.2008.4738279","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738279","url":null,"abstract":"SystemC has evolved from a limited simulation library towards an extensive system design framework since its introduction almost 10 years ago. Currently it is one of the most widely used system design languages and is supported by major EDA vendors. The cost for developing SystemC into a stable and widely adopted system design framework has in our experience been the inherent need of rewriting complex and well-modularized system models with every new SystemC release. In this paper we present our experiences in continuous development of a system level processor model through SystemC version upgrades. The focus is on our latest transition from SystemC 1.1 to version 2.2. In our practical experience, transitions from an older version of SystemC to a newer one have always required rewriting significant amounts, if not most, of the model code. We also experimented with synthesis after the upgrade, and concluded that the synthesis capabilities of SystemC for complex object oriented models are still severely limited at best.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123426736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738278
C. M. Kirchsteiger, C. Trummer, C. Steger, R. Weiss, M. Pistauer
In this work developed in the SIMBA project, we present a novel methodology to reduce the time for System-on-Chip (SoC) verification significantly by automatically generating a verification plan from the specification document. We consider the specification as a series of semi-formal textual use cases, which is a widely accepted document-based hardware specification format and suitable for automatic post-processing. We use an RFID SoC to demonstrate the benefits of our methodology. We show that it significantly reduces the time for functional verification, removes errors in the specification and detects a number of discrepancies between the RFID SoC and the RFID protocol specification.
{"title":"Automatic Verification Plan Generation to Speed up SoC Verification","authors":"C. M. Kirchsteiger, C. Trummer, C. Steger, R. Weiss, M. Pistauer","doi":"10.1109/NORCHP.2008.4738278","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738278","url":null,"abstract":"In this work developed in the SIMBA project, we present a novel methodology to reduce the time for System-on-Chip (SoC) verification significantly by automatically generating a verification plan from the specification document. We consider the specification as a series of semi-formal textual use cases, which is a widely accepted document-based hardware specification format and suitable for automatic post-processing. We use an RFID SoC to demonstrate the benefits of our methodology. We show that it significantly reduces the time for functional verification, removes errors in the specification and detects a number of discrepancies between the RFID SoC and the RFID protocol specification.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121379186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738274
F. Vargas, C. A. Rocha, L. Cristofoli, L. Rocha
We propose a new approach, namely optimized embedded signature monitoring (OESM) to perform on-line control-flow fault detection. The underlined advantage of this approach is the ability to perform a profiling algorithm that analyses the control-flow graph of user program in order to optimize the number of checkpoints (i. e., signatures) to be inserted along with the application code. By optimization, we mean to find, for a given application, the best trade-off between the minimum number of signatures to be inserted in the code, for the maximum fault detection coverage, with the minimum impact in terms of power increase. The embedded signatures are checked at runtime by the processor against compilation-time pre-computed values every time the processor reaches these signature points. Practical experiments have been carried out to demonstrate the OESM benefits when compared to conventional control-flow fault detection approaches.
{"title":"Power-Aware Reliable Embedded Software Design","authors":"F. Vargas, C. A. Rocha, L. Cristofoli, L. Rocha","doi":"10.1109/NORCHP.2008.4738274","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738274","url":null,"abstract":"We propose a new approach, namely optimized embedded signature monitoring (OESM) to perform on-line control-flow fault detection. The underlined advantage of this approach is the ability to perform a profiling algorithm that analyses the control-flow graph of user program in order to optimize the number of checkpoints (i. e., signatures) to be inserted along with the application code. By optimization, we mean to find, for a given application, the best trade-off between the minimum number of signatures to be inserted in the code, for the maximum fault detection coverage, with the minimum impact in terms of power increase. The embedded signatures are checked at runtime by the processor against compilation-time pre-computed values every time the processor reaches these signature points. Practical experiments have been carried out to demonstrate the OESM benefits when compared to conventional control-flow fault detection approaches.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"29 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131721757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738295
O. Schmitz, S. Hampel, C. Orlob, M. Tiebout, I. Rolfes
This paper presents fully differential up-and down-conversion mixers manufactured in a triple well 45 nm standard CMOS process for low voltage UWB TX and RX applications. The proposed circuits both employ the transistor bulk terminal for signal injection. While the RX mixer uses the bulk for switching via threshold voltage modulation, the TX mixer applies the baseband signal to the bulk. Both circuits offer resistive on-chip termination and DC coupled output buffering for measurement purposes. The RX mixer features a maximum conversion gain of 9.4 dB at 2.5 GHz and an input-referred compression point of -13 dBm while the 3-dB low-pass bandwidth is beyond 10 GHz. The TX mixer offers a maximum conversion gain of -8.8 dB at 5.5 GHz and an output-referred compression point of -10.3 dBm. The operational bandwidth ranges from 4.5 GHz to 7 GHz. Both circuits operate at a low voltage power supply of 1.1 V.
{"title":"Low-Voltage Bulk-Driven Mixers in 45nm CMOS for Ultra-Wideband TX and RX","authors":"O. Schmitz, S. Hampel, C. Orlob, M. Tiebout, I. Rolfes","doi":"10.1109/NORCHP.2008.4738295","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738295","url":null,"abstract":"This paper presents fully differential up-and down-conversion mixers manufactured in a triple well 45 nm standard CMOS process for low voltage UWB TX and RX applications. The proposed circuits both employ the transistor bulk terminal for signal injection. While the RX mixer uses the bulk for switching via threshold voltage modulation, the TX mixer applies the baseband signal to the bulk. Both circuits offer resistive on-chip termination and DC coupled output buffering for measurement purposes. The RX mixer features a maximum conversion gain of 9.4 dB at 2.5 GHz and an input-referred compression point of -13 dBm while the 3-dB low-pass bandwidth is beyond 10 GHz. The TX mixer offers a maximum conversion gain of -8.8 dB at 5.5 GHz and an output-referred compression point of -10.3 dBm. The operational bandwidth ranges from 4.5 GHz to 7 GHz. Both circuits operate at a low voltage power supply of 1.1 V.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130713504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738269
Lirong Zheng, M. Nejad, Z. Zou, David S. Mendoza, Zhi Zhang, H. Tenhunen
Next generation RFID towards ubiquitous wireless sensing and identification requires high network throughput along with long operation range and ultra low energy consumption. In this paper, we review future RFID for ubiquitous intelligence and their technology needs from system to device perspectives. As a promising enabling technology, ultra wideband radio (UWB) and its use in various RFID implementations are investigated. A special focus on an UWB/UHF hybrid passive RFID and sensor system with asymmetric wireless links is studied as an example. Unlike conventional RFID systems relying on backscattering and narrowband radio, UWB is introduced as the uplink for tag to reader communication. It enables a high network throughput (2000 tag/sec), high data bandwidth (100 MHz pulse rate), under ultra low power and low cost constraint. The hardware implementation in silicon level is also presented. Finally, applications of the system in intelligent warehouse and fresh food tracker are introduced.
{"title":"Future RFID and Wireless Sensors for Ubiquitous Intelligence","authors":"Lirong Zheng, M. Nejad, Z. Zou, David S. Mendoza, Zhi Zhang, H. Tenhunen","doi":"10.1109/NORCHP.2008.4738269","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738269","url":null,"abstract":"Next generation RFID towards ubiquitous wireless sensing and identification requires high network throughput along with long operation range and ultra low energy consumption. In this paper, we review future RFID for ubiquitous intelligence and their technology needs from system to device perspectives. As a promising enabling technology, ultra wideband radio (UWB) and its use in various RFID implementations are investigated. A special focus on an UWB/UHF hybrid passive RFID and sensor system with asymmetric wireless links is studied as an example. Unlike conventional RFID systems relying on backscattering and narrowband radio, UWB is introduced as the uplink for tag to reader communication. It enables a high network throughput (2000 tag/sec), high data bandwidth (100 MHz pulse rate), under ultra low power and low cost constraint. The hardware implementation in silicon level is also presented. Finally, applications of the system in intelligent warehouse and fresh food tracker are introduced.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132655472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738267
M. Sawan, B. Gosselin, J. Coulombe
This paper covers circuits and systems techniques for the construction of high reliability biosensing and microneurostimulation medical devices. Such implantable devices are dedicated for interconnections to intracortical neural tissues. Low-power high-reliability wireless links are used to power up such implanted devices while bidirectional data are exchanged between these microsystems and external controllers. Global view of main devices will be described, case studies related to monitoring and microstimulation in the primary visual cortex will be discussed, and special attention will be paid to massively parallel recording of neural signals, microstimulation through a large arrays of electrodes and power management of these bioelectronic devices.
{"title":"Learning from the Primary Visual Cortex to Recover Vision for the Blind by Microstimulation","authors":"M. Sawan, B. Gosselin, J. Coulombe","doi":"10.1109/NORCHP.2008.4738267","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738267","url":null,"abstract":"This paper covers circuits and systems techniques for the construction of high reliability biosensing and microneurostimulation medical devices. Such implantable devices are dedicated for interconnections to intracortical neural tissues. Low-power high-reliability wireless links are used to power up such implanted devices while bidirectional data are exchanged between these microsystems and external controllers. Global view of main devices will be described, case studies related to monitoring and microstimulation in the primary visual cortex will be discussed, and special attention will be paid to massively parallel recording of neural signals, microstimulation through a large arrays of electrodes and power management of these bioelectronic devices.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738296
J. Wernehag, H. Sjöland
A new passive subharmonic mixer topology is presented and compared to a previously published passive topology. The comparison is conducted using simulations at 30 GHz with a 90-nm CMOS design kit. The advantage of the new passive subharmonic mixer is that it only requires a differential local oscillator (LO) signal, compared to the previously published mixer that requires a quadrature LO signal. The mixer consists of two cascaded passive mixers with an interstage second order filter suppressing harmonics while providing some 10 dB of voltage gain at the LO frequency. The noise performance of the differential mixer is slightly worse than for the quadrature one, with a simulated down conversion SSB NF of 10 dB compared to 7 dB. The voltage conversion gain is - 1 dB for both mixers, all with a 1 V LO amplitude.
{"title":"A 30 GHz 90-nm CMOS Passive Subharmonic Mixer with 15 GHz Differential LO","authors":"J. Wernehag, H. Sjöland","doi":"10.1109/NORCHP.2008.4738296","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738296","url":null,"abstract":"A new passive subharmonic mixer topology is presented and compared to a previously published passive topology. The comparison is conducted using simulations at 30 GHz with a 90-nm CMOS design kit. The advantage of the new passive subharmonic mixer is that it only requires a differential local oscillator (LO) signal, compared to the previously published mixer that requires a quadrature LO signal. The mixer consists of two cascaded passive mixers with an interstage second order filter suppressing harmonics while providing some 10 dB of voltage gain at the LO frequency. The noise performance of the differential mixer is slightly worse than for the quadrature one, with a simulated down conversion SSB NF of 10 dB compared to 7 dB. The voltage conversion gain is - 1 dB for both mixers, all with a 1 V LO amplitude.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115430623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738308
Peng Wang, F. Jonsson, H. Tenhunen, Dian Zhou, Lirong Zheng
This paper analyzes architectures of the low noise amplifier (LNA) for orthogonal-frequency-division-multiplexing ultra-wideband (OFDM-UWB) application. Until now, most UWB LNA implementations are focusing how to realize a single LNA covering the whole frequency band. In this work three popular wide-band LNA architectures are compared to a proposed parallel LNA architecture in which different amplifiers cover different frequency bands. Our study reveals that by reusing the source degenerated inductor between the different frequency bands, the parallel LNA architecture can achieve better performance than the single wide-band LNA (S11≪-10 dB, voltage gain≫15 dB, NF≪4.5 dB, power consumption≪10 mW) at the expense of a slightly increased circuit area.
{"title":"Low Noise Amplifier Architecture Analysis for OFDM-UWB System in 0.18μm CMOS","authors":"Peng Wang, F. Jonsson, H. Tenhunen, Dian Zhou, Lirong Zheng","doi":"10.1109/NORCHP.2008.4738308","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738308","url":null,"abstract":"This paper analyzes architectures of the low noise amplifier (LNA) for orthogonal-frequency-division-multiplexing ultra-wideband (OFDM-UWB) application. Until now, most UWB LNA implementations are focusing how to realize a single LNA covering the whole frequency band. In this work three popular wide-band LNA architectures are compared to a proposed parallel LNA architecture in which different amplifiers cover different frequency bands. Our study reveals that by reusing the source degenerated inductor between the different frequency bands, the parallel LNA architecture can achieve better performance than the single wide-band LNA (S11≪-10 dB, voltage gain≫15 dB, NF≪4.5 dB, power consumption≪10 mW) at the expense of a slightly increased circuit area.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116032815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738324
T. Sundstrom, A. Alvandpour
A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS, avoids traditional power, speed and accuracy trade-offs by using comparator redundancy with power-gating capabilities. Redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators. Measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 gate-able comparators, the ADC achieves 4.0 effective number of bits.
{"title":"A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS","authors":"T. Sundstrom, A. Alvandpour","doi":"10.1109/NORCHP.2008.4738324","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738324","url":null,"abstract":"A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS, avoids traditional power, speed and accuracy trade-offs by using comparator redundancy with power-gating capabilities. Redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators. Measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 gate-able comparators, the ADC achieves 4.0 effective number of bits.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128259459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/NORCHP.2008.4738268
M. Min
Methods for reducing the complexity of both - signal processing algorithms and hardware solutions - are proposed for performing the fast impedance spectroscopy in dynamic conditions. Minimal computational resources and low power consumption are the prerequisites for applications in embedded systems. Simple techniques for both - synthesizing of excitation waveforms and processing of response signals - are developed. Only a few-level quantization of signals is implemented and their normalized levels as +1, -1, and 0 are preferred.
{"title":"Embedded Signal Processing in Impedance Spectroscopy","authors":"M. Min","doi":"10.1109/NORCHP.2008.4738268","DOIUrl":"https://doi.org/10.1109/NORCHP.2008.4738268","url":null,"abstract":"Methods for reducing the complexity of both - signal processing algorithms and hardware solutions - are proposed for performing the fast impedance spectroscopy in dynamic conditions. Minimal computational resources and low power consumption are the prerequisites for applications in embedded systems. Simple techniques for both - synthesizing of excitation waveforms and processing of response signals - are developed. Only a few-level quantization of signals is implemented and their normalized levels as +1, -1, and 0 are preferred.","PeriodicalId":199376,"journal":{"name":"2008 NORCHIP","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129381006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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