Y. Hirose, M. Saito, Hiroyuki Utsumi, Toshiaki Saruwatari, A. Suga, T. Sukemura, H. Takahashi, H. Miyake, Y. Takebe, M. Kimura, H. Okano, Masayuki Tsuji, T. Satoh, T. Katayama
{"title":"A 4-way VLIW embedded processor and its companion chip","authors":"Y. Hirose, M. Saito, Hiroyuki Utsumi, Toshiaki Saruwatari, A. Suga, T. Sukemura, H. Takahashi, H. Miyake, Y. Takebe, M. Kimura, H. Okano, Masayuki Tsuji, T. Satoh, T. Katayama","doi":"10.1109/APASIC.2000.896984","DOIUrl":null,"url":null,"abstract":"A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating pipeline and media pipeline has 2-parallel and 4-parallel SIMD mechanisms, respectively. The processor equips separate instruction and data caches; each of 16 KB size and 4-way set associative. 6.7 M transistors are integrated in an area of 7.5 mm/spl times/7.5 mm. We also developed companion chip which is used together with the processor. Companion chip is fabricated using a 0.25 /spl mu/m 4-layer-metal CMOS process.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896984","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating pipeline and media pipeline has 2-parallel and 4-parallel SIMD mechanisms, respectively. The processor equips separate instruction and data caches; each of 16 KB size and 4-way set associative. 6.7 M transistors are integrated in an area of 7.5 mm/spl times/7.5 mm. We also developed companion chip which is used together with the processor. Companion chip is fabricated using a 0.25 /spl mu/m 4-layer-metal CMOS process.
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