S. Seo, T. Moon, J.H. Kim, K. Kwon, J. Jeon, S.H. Hwang
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引用次数: 9
Abstract
This paper presents a fault-tolerant gateway embedded system that uses two micro-controllers. One microcontroller performs the main function of achieving a gateway, often called by the main micro-controller. In contrast, another plays the role of checker for the main micro-controller, and is called the sub micro-controller. To achieve fault-tolerance, the checker monitors the state of the main micro-controller. In this paper, we propose hardware architecture for fault-tolerance and evaluate the performance of the proposed system.