A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs

Abstract

An on-chip/off-chip hybrid transposition table (TT) is proposed to implement artificial intelligence functions in mobile platforms. In order to meet the power consumption and throughput requirements for realizing the intelligence functions in real-time, the TT is playing a key role to prevent the duplicated evaluations in a tree search by storing search results. Three key features, 1) On-chip/off-chip hybrid TT architecture, 2) On-chip buffer cache, and 3) Progress-based entry replacement policy, are proposed to overcome the design challenges (hit rate, latency and off-chip bandwidth) for implementing the TT. The proposed hybrid TT is fabricated in a 65nm CMOS technology, and achieves 35% hit ratio and 220ns latency with only 1.41mW power consumption and 2.9MB/s off-chip memory bandwidth.