Design Technique for Ultra-Wideband Balanced Frequency Doublers

Abstract

This work presents an ultra-wideband, balanced frequency multiplier and amplifier combination, implemented in a 130 nm SiGe BiCMOS process. A design technique for balanced, extreme bandwidth frequency multiplier is introduced. The topology is then combined with an inductively peaked, differential wideband amplifier to address the required bandwidth, the output power and to suppress the common mode signal. The designed circuit operates in a continuous 3 GHz to 40 GHz output frequency range, has an average conversion loss of 3 dB, the rejection ratios of fundamental and 3rd harmonic frequencies are better than 34 dBc and 48 dBc respectively and it consumes 21 mA from a 3 V power source. To the best knowledge of the author, this work strongly outperforms the state of the art in terms of the fractional bandwidth.