Comparative Analysis of Various Design Implementations of CLA Carry Chains

Abstract

This paper presents a comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count. Two different design implementations of CLA carry generation circuit are discussed and compared based on their speed and transistor count. The representative designs compared are Complementary Metal Oxide Semiconductor (CMOS) Conventional CLA (CCLA) carry generation structure and proposed structure of CLA carry generation, named VpAn. To yield optimized delay for the proposed VpAn Design, transistor resizing has been done. A comprehensive comparison and analysis of performance of four, eight and sixteen bit carry chains are carried out. All the schematics of the CLA carry chains are designed using 0.25um process. The simulations of the schematics of CMOS conventional CLA generation circuits and the proposed CLA carry generation designs are performed using LTspice based on 250nm CMOS technology and 2.5V supply voltage to yield realistic rise and fall times. The speed of each circuit is evaluated and our proposed model reduces the propagation delay by 75% compared to the results of CCLA before sizing. This paper establishes, how the physical implementation of circuits relate to their performance.