Pub Date : 2018-10-18DOI: 10.1109/EIT.2018.8500180
A. Ahamed, H. Vakilzadian
Intelligent transportation systems (ITS) are becoming more popular due to the demand for advanced cyber-physical systems and comfort applications and services needed for use in autonomous vehicles. Vehicular ad hoc Networks (VANETs) are an essential part of ITS, as they support vehicle-to-vehicle and vehicle-to-infrastructure data communication. The performance of a VANET solely depends on the routing protocols in the network layer, which provide efficient and effective data communication. In this paper, we survey the most recent issues surrounding efficient routing protocols that are suitable for VANETs. We also address the pros and cons of these protocols in terms of scalability, quality of services, security and privacy, energy efficiency, transmission bandwidth limitation, and broadcasting issues.
{"title":"Issues and Challenges in VANET Routing Protocols","authors":"A. Ahamed, H. Vakilzadian","doi":"10.1109/EIT.2018.8500180","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500180","url":null,"abstract":"Intelligent transportation systems (ITS) are becoming more popular due to the demand for advanced cyber-physical systems and comfort applications and services needed for use in autonomous vehicles. Vehicular ad hoc Networks (VANETs) are an essential part of ITS, as they support vehicle-to-vehicle and vehicle-to-infrastructure data communication. The performance of a VANET solely depends on the routing protocols in the network layer, which provide efficient and effective data communication. In this paper, we survey the most recent issues surrounding efficient routing protocols that are suitable for VANETs. We also address the pros and cons of these protocols in terms of scalability, quality of services, security and privacy, energy efficiency, transmission bandwidth limitation, and broadcasting issues.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125725266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-18DOI: 10.1109/EIT.2018.8500237
Md. Naimur Rahman, M. Islam, J. S. Mandeep, N. Misran
This paper presents the architecture and exploration of a compact, circulated double Psi-shaped microstrip patch antenna for Ku-band satellite applications. The antenna is composed of the double Psi-shaped patch in opposite focus which is circulated with a ring. The antenna size is $24 mathbf{mm} times 18 mathbf{mm}$ and the prototype is imprinted on Rogers RT/duroid 5880 materials with the depth of 1.57 mm. The substrate has a relative permittivity of 2.2 and the dielectric constant of 0.0009. The excitation is supplied through a 500 microstrip line. The performance of the presented antenna has been simulated and verified with the High-Frequency Structural Simulator (HFSS). The results depict that the antenna covers the frequency spectrum 14.6 - 17.4 GHz (Ku band) with 10 dB return loss. The antenna has a 4.40 dBi maximum gain with stable radiation patterns throughout the operating band which makes the proposed antenna compatible for the satellite application in Ku-band.
{"title":"Depiction of a Circulated Double Psi-Shaped Microstrip Antenna for Ku-Band Satellite Applications","authors":"Md. Naimur Rahman, M. Islam, J. S. Mandeep, N. Misran","doi":"10.1109/EIT.2018.8500237","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500237","url":null,"abstract":"This paper presents the architecture and exploration of a compact, circulated double Psi-shaped microstrip patch antenna for Ku-band satellite applications. The antenna is composed of the double Psi-shaped patch in opposite focus which is circulated with a ring. The antenna size is $24 mathbf{mm} times 18 mathbf{mm}$ and the prototype is imprinted on Rogers RT/duroid 5880 materials with the depth of 1.57 mm. The substrate has a relative permittivity of 2.2 and the dielectric constant of 0.0009. The excitation is supplied through a 500 microstrip line. The performance of the presented antenna has been simulated and verified with the High-Frequency Structural Simulator (HFSS). The results depict that the antenna covers the frequency spectrum 14.6 - 17.4 GHz (Ku band) with 10 dB return loss. The antenna has a 4.40 dBi maximum gain with stable radiation patterns throughout the operating band which makes the proposed antenna compatible for the satellite application in Ku-band.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127873093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-18DOI: 10.1109/EIT.2018.8500118
Yanlin Zhou, Ryan Anderson, H. Vakilzadian, D. Moeller, Andreas Deutschmann
This paper devises a dynamic queueing model for the airport check-in process. The airport scheduling system is highly dynamic, for it is inherently highly dimensional and takes input from a various of involved parties, i.e., passengers, airport staff, airport infrastructure, airline companies and etc. The proposed model presents a top-down focus to guarantee a reliable, punctual and efficient check-in scheduling scheme and is later generalized from bottom-up to be applicable for other processes. In our work, we design a flow logic and derive the framework analytically with MATLAB. Then the simulation of service time and arrival distribution are provided. In the Experiment, the real data collected from Hamburg International Airport was fed into the model and achieved satisfying results. Both analytically and experimentally, we prove that our model is capable of solving dynamic queueing problems.
{"title":"Developing A Dynamic Queueing Model for The Airport Check-in Process","authors":"Yanlin Zhou, Ryan Anderson, H. Vakilzadian, D. Moeller, Andreas Deutschmann","doi":"10.1109/EIT.2018.8500118","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500118","url":null,"abstract":"This paper devises a dynamic queueing model for the airport check-in process. The airport scheduling system is highly dynamic, for it is inherently highly dimensional and takes input from a various of involved parties, i.e., passengers, airport staff, airport infrastructure, airline companies and etc. The proposed model presents a top-down focus to guarantee a reliable, punctual and efficient check-in scheduling scheme and is later generalized from bottom-up to be applicable for other processes. In our work, we design a flow logic and derive the framework analytically with MATLAB. Then the simulation of service time and arrival distribution are provided. In the Experiment, the real data collected from Hamburg International Airport was fed into the model and achieved satisfying results. Both analytically and experimentally, we prove that our model is capable of solving dynamic queueing problems.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125177665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/siprocess.2018.8600457
Ahmed El-Yamany, H. Fouad, Youssef Raffat
Camera model identification has been attracting a lot of attention lately, as a powerful forensic method. With the promising breakthroughs in the artificial intelligence applications, such systems were revisited to increase the expected accuracy or to solve the still persisting deadlocks. One of the most still-to-be-solved dilemmas is the image manipulations effect on the overall accuracy of the identification systems. A huge degradation in the performance is noticed, when images are post-processed using commonly used methods as compression, scaling and contrast enhancement. Using the state of the art Convolutional Neural Network (CNN) architecture proposed by Bayar et al to estimate the manipulation parameters, and dedicated feature extractor models to estimate the source camera. Multiplexers are used to shift the input image between the dedicated models through the output of the CNNs. Our proposed methods significantly outperform state of the art methods in the literature, especially in case of heavy compression and down sampling. The images used for testing were extracted from 10 different cameras, including different models from the same manufacturer. Different devices were used to investigate the methodology robustness. Moreover, such generic approach could revolutionary change the whole design methodology for camera model identification systems.
{"title":"A Generic Approach CNN-Based Camera Identification for Manipulated Images","authors":"Ahmed El-Yamany, H. Fouad, Youssef Raffat","doi":"10.1109/siprocess.2018.8600457","DOIUrl":"https://doi.org/10.1109/siprocess.2018.8600457","url":null,"abstract":"Camera model identification has been attracting a lot of attention lately, as a powerful forensic method. With the promising breakthroughs in the artificial intelligence applications, such systems were revisited to increase the expected accuracy or to solve the still persisting deadlocks. One of the most still-to-be-solved dilemmas is the image manipulations effect on the overall accuracy of the identification systems. A huge degradation in the performance is noticed, when images are post-processed using commonly used methods as compression, scaling and contrast enhancement. Using the state of the art Convolutional Neural Network (CNN) architecture proposed by Bayar et al to estimate the manipulation parameters, and dedicated feature extractor models to estimate the source camera. Multiplexers are used to shift the input image between the dedicated models through the output of the CNNs. Our proposed methods significantly outperform state of the art methods in the literature, especially in case of heavy compression and down sampling. The images used for testing were extracted from 10 different cameras, including different models from the same manufacturer. Different devices were used to investigate the methodology robustness. Moreover, such generic approach could revolutionary change the whole design methodology for camera model identification systems.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"391 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122848748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-10DOI: 10.1109/EIT.2018.8500248
D. Möller, H. Vakilzadian, Andreas Deutschmann
The paper introduce into an intelligent system application approach which make use of the Internet of Things (IoT) paradigm, a cutting-edge innovation in today's global economy and a key technology within the digital transformation. Digital transformation allows information and communication technology systems to work at a higher degree of connected system behavior that has been invisible embedded within the digital ecosystem. Together with the advent of increasing capabilities of intelligent systems users are able to monitor and control their domain specific processes on demand such as luggage handling at airports. In this context it is obvious to merge the required wireless communication of the domain specific ecosystem application for seamless connectivity of the intelligent system process requirements. However, the technological advances of the different types of application processes determine security threats of the specific intelligent systems they face, which will require developing adequate security solutions.
{"title":"Intelligent System Demonstrator for Secure Luggage Handling","authors":"D. Möller, H. Vakilzadian, Andreas Deutschmann","doi":"10.1109/EIT.2018.8500248","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500248","url":null,"abstract":"The paper introduce into an intelligent system application approach which make use of the Internet of Things (IoT) paradigm, a cutting-edge innovation in today's global economy and a key technology within the digital transformation. Digital transformation allows information and communication technology systems to work at a higher degree of connected system behavior that has been invisible embedded within the digital ecosystem. Together with the advent of increasing capabilities of intelligent systems users are able to monitor and control their domain specific processes on demand such as luggage handling at airports. In this context it is obvious to merge the required wireless communication of the domain specific ecosystem application for seamless connectivity of the intelligent system process requirements. However, the technological advances of the different types of application processes determine security threats of the specific intelligent systems they face, which will require developing adequate security solutions.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117117483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-03DOI: 10.1109/EIT.2018.8500127
Yazid Alkraimeen, P. Gómez
Internal winding faults are the most common cause of failure in power transformers. The complicated electrical and geometrical configuration of transformers makes it difficult to produce models able to predict their behavior under transient conditions in an accurate and efficient manner. Internal fault analysis of windings requires a detailed (turn-by-turn) modeling approach that results in very large systems that can be difficult to define and computationally expensive. In addition, in many cases the fault analysis does not require from measurements at all turns, but only at the turns related to the fault condition. The purpose of this work is to describe a modeling approach for internal fault analysis of transformer windings using a frequency domain approach in combination with Kron's network reduction to preserve only the nodes of particular interest, and the numerical inverse Laplace transform to obtain the transient response of the system in the time domain. A prototype transformer winding with 2000 turns is used for this purpose. Comparisons between the open and short circuit faults for the complete network system and the equivalent reduced network provide the same results considering a very small portion of the original system's size.
{"title":"Internal Fault Analysis in Disk-Type Transformer Winding Using Network Reduction","authors":"Yazid Alkraimeen, P. Gómez","doi":"10.1109/EIT.2018.8500127","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500127","url":null,"abstract":"Internal winding faults are the most common cause of failure in power transformers. The complicated electrical and geometrical configuration of transformers makes it difficult to produce models able to predict their behavior under transient conditions in an accurate and efficient manner. Internal fault analysis of windings requires a detailed (turn-by-turn) modeling approach that results in very large systems that can be difficult to define and computationally expensive. In addition, in many cases the fault analysis does not require from measurements at all turns, but only at the turns related to the fault condition. The purpose of this work is to describe a modeling approach for internal fault analysis of transformer windings using a frequency domain approach in combination with Kron's network reduction to preserve only the nodes of particular interest, and the numerical inverse Laplace transform to obtain the transient response of the system in the time domain. A prototype transformer winding with 2000 turns is used for this purpose. Comparisons between the open and short circuit faults for the complete network system and the equivalent reduced network provide the same results considering a very small portion of the original system's size.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123714998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-03DOI: 10.1109/EIT.2018.8500194
Hadeel Mohammed Jawad, D. Laski-Smith, Samir Tout
Computer programming is not easy and many educators and developers have been trying to create a development environment that makes programming easier and more interesting for K12 students. This paper demonstrates one of these efforts by introducing a newly developed educational environment that could help high school students learn computer programming language. Code Genie was designed to integrate art, animation, and code sharing in teaching programming. Using this web-based learning environment, students can learn how to write a program in a JavaScript language, and how to produce artwork from coding, then share it with others. JavaScript was chosen for its popularity, simplicity and because it is a real programming language that is currently used by software developers who create real software products. The Code Genie learning environment and the motivation behind developing it for high school students are discussed in this paper. It was tested during three coding workshops. Student responses to the tool's usefulness and ease of use will be explained.
{"title":"The Code Genie Programming Environment","authors":"Hadeel Mohammed Jawad, D. Laski-Smith, Samir Tout","doi":"10.1109/EIT.2018.8500194","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500194","url":null,"abstract":"Computer programming is not easy and many educators and developers have been trying to create a development environment that makes programming easier and more interesting for K12 students. This paper demonstrates one of these efforts by introducing a newly developed educational environment that could help high school students learn computer programming language. Code Genie was designed to integrate art, animation, and code sharing in teaching programming. Using this web-based learning environment, students can learn how to write a program in a JavaScript language, and how to produce artwork from coding, then share it with others. JavaScript was chosen for its popularity, simplicity and because it is a real programming language that is currently used by software developers who create real software products. The Code Genie learning environment and the motivation behind developing it for high school students are discussed in this paper. It was tested during three coding workshops. Student responses to the tool's usefulness and ease of use will be explained.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129660846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-03DOI: 10.1109/EIT.2018.8500112
Naga Spandana Muppaneni, Steve C. Chiu, V. Kantabutra, Farshad Dailami
This paper presents a comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count. Two different design implementations of CLA carry generation circuit are discussed and compared based on their speed and transistor count. The representative designs compared are Complementary Metal Oxide Semiconductor (CMOS) Conventional CLA (CCLA) carry generation structure and proposed structure of CLA carry generation, named VpAn. To yield optimized delay for the proposed VpAn Design, transistor resizing has been done. A comprehensive comparison and analysis of performance of four, eight and sixteen bit carry chains are carried out. All the schematics of the CLA carry chains are designed using 0.25um process. The simulations of the schematics of CMOS conventional CLA generation circuits and the proposed CLA carry generation designs are performed using LTspice based on 250nm CMOS technology and 2.5V supply voltage to yield realistic rise and fall times. The speed of each circuit is evaluated and our proposed model reduces the propagation delay by 75% compared to the results of CCLA before sizing. This paper establishes, how the physical implementation of circuits relate to their performance.
{"title":"Comparative Analysis of Various Design Implementations of CLA Carry Chains","authors":"Naga Spandana Muppaneni, Steve C. Chiu, V. Kantabutra, Farshad Dailami","doi":"10.1109/EIT.2018.8500112","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500112","url":null,"abstract":"This paper presents a comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count. Two different design implementations of CLA carry generation circuit are discussed and compared based on their speed and transistor count. The representative designs compared are Complementary Metal Oxide Semiconductor (CMOS) Conventional CLA (CCLA) carry generation structure and proposed structure of CLA carry generation, named VpAn. To yield optimized delay for the proposed VpAn Design, transistor resizing has been done. A comprehensive comparison and analysis of performance of four, eight and sixteen bit carry chains are carried out. All the schematics of the CLA carry chains are designed using 0.25um process. The simulations of the schematics of CMOS conventional CLA generation circuits and the proposed CLA carry generation designs are performed using LTspice based on 250nm CMOS technology and 2.5V supply voltage to yield realistic rise and fall times. The speed of each circuit is evaluated and our proposed model reduces the propagation delay by 75% compared to the results of CCLA before sizing. This paper establishes, how the physical implementation of circuits relate to their performance.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121499842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-03DOI: 10.1109/EIT.2018.8500227
T. Khan
The standard deviation can measure the spread out of a set of numbers and entropy can measure the randomness. However, they do not consider the order of the numbers. This can lead to misleading results where the order of the numbers is vital. An image is a set of numbers (i.e. pixel values) that is sensitive to order. In this paper, an efficient method for measuring the fluctuation is proposed considering the order of the numbers. The proposed method sums up the changes of consecutive numbers and can be used in image processing applications. Simulation shows that the proposed method is 8 to 33 times faster than other related works.
{"title":"An Efficient Fluctuation Measurement Method in Image Processing Considering Order","authors":"T. Khan","doi":"10.1109/EIT.2018.8500227","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500227","url":null,"abstract":"The standard deviation can measure the spread out of a set of numbers and entropy can measure the randomness. However, they do not consider the order of the numbers. This can lead to misleading results where the order of the numbers is vital. An image is a set of numbers (i.e. pixel values) that is sensitive to order. In this paper, an efficient method for measuring the fluctuation is proposed considering the order of the numbers. The proposed method sums up the changes of consecutive numbers and can be used in image processing applications. Simulation shows that the proposed method is 8 to 33 times faster than other related works.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126471106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-03DOI: 10.1109/EIT.2018.8500096
Leonardo C. Resende, D. B. Haddad, M. R. Petraglia
In adaptive filtering, there is usually a trade-off between the speed of convergence and the accuracy of the learning procedure. Recently, variable step-size algorithms and coefficient vector reusing schemes were proposed to solve this trade-off. This paper presents a new adaptive filtering algorithm that combines both strategies to achieve fast convergence speed and low steady-state misadjustment simultaneously. In the proposed algorithm, the error signal is used to dynamically adjust the step-size and the reusing order in each iteration. Simulation results demonstrate better performance of the proposed algorithm when compared to previously proposed approaches.
{"title":"A Variable Step-Size NLMS Algorithm with Adaptive Coefficient Vector Reusing","authors":"Leonardo C. Resende, D. B. Haddad, M. R. Petraglia","doi":"10.1109/EIT.2018.8500096","DOIUrl":"https://doi.org/10.1109/EIT.2018.8500096","url":null,"abstract":"In adaptive filtering, there is usually a trade-off between the speed of convergence and the accuracy of the learning procedure. Recently, variable step-size algorithms and coefficient vector reusing schemes were proposed to solve this trade-off. This paper presents a new adaptive filtering algorithm that combines both strategies to achieve fast convergence speed and low steady-state misadjustment simultaneously. In the proposed algorithm, the error signal is used to dynamically adjust the step-size and the reusing order in each iteration. Simulation results demonstrate better performance of the proposed algorithm when compared to previously proposed approaches.","PeriodicalId":188414,"journal":{"name":"2018 IEEE International Conference on Electro/Information Technology (EIT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125718102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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