A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221199

S. Verma, Junfeng Xu, T. Lee

引用次数: 0

Abstract

A frequency-synthesis technique which extracts the N/sup th/ harmonic from an N-stage oscillator is presented. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled, single-ended three-stage ring oscillators has been fabricated in 0.24 /spl mu/m CMOS, designed to work in the 902-928 MHz ISM band (US and Canada). It provides two outputs: one at the normal operating frequency of the oscillator, and another at three times that frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.

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用于低功率频率合成的乘3耦合环振荡器

提出了一种从N级振荡器中提取N/sup / harmonic的频率合成技术。估计了这种振荡器可达到的最大电压摆幅。为了研究这一技术，在0.24 /spl mu/m CMOS中制作了一个带有两个180/spl度/耦合单端三级环形振荡器的乘3电路，设计用于902-928 MHz ISM频段(美国和加拿大)。它提供两个输出:一个是振荡器的正常工作频率，另一个是振荡器正常工作频率的三倍。该电路可以在低至1.3 V的电压下工作，同时消耗210 /spl mu/A的电流。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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