High-Voltage a-IGZO Thin Film Transistor with the Symmetrical Stair Gate-Dielectric Structure

Abstract

We fabricated the a-IGZO transistors with the symmetrical stair gate-dielectric structure. The electrical properties of the studied devices are examined in detail. Both the source and drain breakdown voltage (VBD, GS and VBD, GD) of over 60 V are obtained with the Lstair of 3 μm. It is observed that the threshold voltage (Vth) and subthreshold voltage have a negligible variation with the length of the stair region (Lstair). The transconductance (gm) slightly decreases with the Lstair because the gate capacitance is smaller in the device with the symmetrical stair structure. The distribution of the on-resistance (Ron) of the stair region (Mstair) is demonstrated. The simulation is performed to further understand the operation mechanism of the symmetrical stair structure a-IGZO TFTs.