Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915715
B. Yeoh, M.H. Thor, L.S. Gan, Y. Chan, S. Goh
Dynamic Laser Stimulation (DLS) techniques have met with great success to debug integrated circuit (IC) soft failure. Laser assisted device alteration (LADA) is one of the DLS technique well-established to tackle speed-path failure and analysis of defect-free performance limiting circuits. In this work, we discuss atypical LADA analysis to localize system-on-chip (SOC) memory manufacturing soft and hard defects.
{"title":"LADA methodologies to localize embedded memory failure","authors":"B. Yeoh, M.H. Thor, L.S. Gan, Y. Chan, S. Goh","doi":"10.1109/IPFA55383.2022.9915715","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915715","url":null,"abstract":"Dynamic Laser Stimulation (DLS) techniques have met with great success to debug integrated circuit (IC) soft failure. Laser assisted device alteration (LADA) is one of the DLS technique well-established to tackle speed-path failure and analysis of defect-free performance limiting circuits. In this work, we discuss atypical LADA analysis to localize system-on-chip (SOC) memory manufacturing soft and hard defects.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115155799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915735
Deruo Cheng, Yee-Yang Tee, Jingsi Song, Yiqiong Shi, Tong Lin, B. Gwee
The emergence of data science and deep learning has enabled the automated recognition of circuit elements from the microscopic images of delayered Integrated Circuit (IC) devices, and has greatly improved the efficiency of overall functional analysis flow for hardware security. However, due to the high complexity of delayering the manufactured IC devices and the imaging imperfections in modern ICs, the acquired microscopic images usually contain unforeseeable variations even for the same types of circuit elements. As a result, the deep learning model which is typically trained with a very limited set of labelled images suffers from inefficacy on generalizing to unseen images, which further causes errors for subsequent analysis. Data augmentation techniques, which virtually introduce data variations and increase the data amount by applying different image transformations, are thus widely used during the training of deep learning models for IC image analysis. In this paper, we propose a Semantic-Masked Intensity Augmentation (SMIA) technique with a deep-learning-based framework to analyze the microscopic images acquired from a delayered Field-Programmable Gate Arrays (FPGA) device. Different from the commonly-used intensity augmentation techniques which apply transformations to the image pixels according to their original intensities, our proposed SMIA considers the semantic context of the image pixels by applying different intensity transformations according to pixel-level semantic masks. With experiments on segmenting metal lines from the metal layer images of a targeted FPGA, our proposed SMIA demonstrates better performance and higher stability than the existing intensity augmentation techniques.
{"title":"Semantic-Masked Intensity Augmentation for Deep Learning-based Analysis of FPGA Images","authors":"Deruo Cheng, Yee-Yang Tee, Jingsi Song, Yiqiong Shi, Tong Lin, B. Gwee","doi":"10.1109/IPFA55383.2022.9915735","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915735","url":null,"abstract":"The emergence of data science and deep learning has enabled the automated recognition of circuit elements from the microscopic images of delayered Integrated Circuit (IC) devices, and has greatly improved the efficiency of overall functional analysis flow for hardware security. However, due to the high complexity of delayering the manufactured IC devices and the imaging imperfections in modern ICs, the acquired microscopic images usually contain unforeseeable variations even for the same types of circuit elements. As a result, the deep learning model which is typically trained with a very limited set of labelled images suffers from inefficacy on generalizing to unseen images, which further causes errors for subsequent analysis. Data augmentation techniques, which virtually introduce data variations and increase the data amount by applying different image transformations, are thus widely used during the training of deep learning models for IC image analysis. In this paper, we propose a Semantic-Masked Intensity Augmentation (SMIA) technique with a deep-learning-based framework to analyze the microscopic images acquired from a delayered Field-Programmable Gate Arrays (FPGA) device. Different from the commonly-used intensity augmentation techniques which apply transformations to the image pixels according to their original intensities, our proposed SMIA considers the semantic context of the image pixels by applying different intensity transformations according to pixel-level semantic masks. With experiments on segmenting metal lines from the metal layer images of a targeted FPGA, our proposed SMIA demonstrates better performance and higher stability than the existing intensity augmentation techniques.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122721037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915714
N. Herfurth, E. Amini, M. Lisker, Jean-Pierre Seifert, C. Boit
IC security is not ensured until the chip backside is fully protected. This paper presents a comprehensive and VLSI-compatible protection structure to secure integrated circuits (ICs) against all types of physical and optical attacks targeting the IC via the chip backside. The novel method of protecting the IC structure is provided by outsourcing the protection scheme onto a dedicated protection wafer. This protection wafer is then irreversibly bonded to the IC. This process can be performed at wafer level, realising a VLSI-compatible protection scheme. An example integration based on the new approach is described and discussed in detail.The protection wafer consists of a highly doped silicon substrate forming an optical opaque layer. The protection wafer is irreversibly bonded to the IC and electrically contacted by through silicon vias (TSVs). Integrity of the wafer-stack is verified by an electro-optical process. The protection wafer contains several photon-emitting devices. Several p-n junctions on the circuit side of the protected IC sense the optical signals generated by the photon emitting devices on the protection wafer.
{"title":"A scalable & comprehensive resilience concept against optical & physical IC backside attacks","authors":"N. Herfurth, E. Amini, M. Lisker, Jean-Pierre Seifert, C. Boit","doi":"10.1109/IPFA55383.2022.9915714","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915714","url":null,"abstract":"IC security is not ensured until the chip backside is fully protected. This paper presents a comprehensive and VLSI-compatible protection structure to secure integrated circuits (ICs) against all types of physical and optical attacks targeting the IC via the chip backside. The novel method of protecting the IC structure is provided by outsourcing the protection scheme onto a dedicated protection wafer. This protection wafer is then irreversibly bonded to the IC. This process can be performed at wafer level, realising a VLSI-compatible protection scheme. An example integration based on the new approach is described and discussed in detail.The protection wafer consists of a highly doped silicon substrate forming an optical opaque layer. The protection wafer is irreversibly bonded to the IC and electrically contacted by through silicon vias (TSVs). Integrity of the wafer-stack is verified by an electro-optical process. The protection wafer contains several photon-emitting devices. Several p-n junctions on the circuit side of the protected IC sense the optical signals generated by the photon emitting devices on the protection wafer.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"76 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123218337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915718
F. Stellari, L. Ocola, E. Wu, T. Ando, P. Song
In this paper, we study the photon emission from filaments formed in amorphous HfO2 Resistive Random-Access Memory (ReRAM) cells and compare it to previous results from crystalline cells. Both a CCD and an InGaAs camera are used to observe the photon emission in set/reset state using forward/reverse bias voltage. An electric field model and a uniform Poisson spatial distribution model can be used to model the photon emission on both types of cell types.
{"title":"Photon Emission Microscopy of Amorphous HfO2 ReRAM Cells","authors":"F. Stellari, L. Ocola, E. Wu, T. Ando, P. Song","doi":"10.1109/IPFA55383.2022.9915718","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915718","url":null,"abstract":"In this paper, we study the photon emission from filaments formed in amorphous HfO2 Resistive Random-Access Memory (ReRAM) cells and compare it to previous results from crystalline cells. Both a CCD and an InGaAs camera are used to observe the photon emission in set/reset state using forward/reverse bias voltage. An electric field model and a uniform Poisson spatial distribution model can be used to model the photon emission on both types of cell types.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"17 2-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132483538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915709
A. Rummel, Greg M. Johnson
An intentionally overstressed fin defect was created in 5 nm technology. EBIC analysis with 0.5 kV electron beam stimulation enabled early detection of the defect during overstress experiments. EBIRCH analysis, again at 0.5 kV was able to isolate the exact spot of the fail in a multi-fin device. Additional EBIC scans at various kVs were also able to isolate the failing fin, located close to the EBIRCH spot, and provided insights on how to use Monte Carlo scattering models to predict the optimal beam energy to find defects via EBIC. This approach could be applied to fails in 5 nm or systems with delicate structures.
{"title":"Optimizing EBAC / EBIRCH analysis in 5 nm technology","authors":"A. Rummel, Greg M. Johnson","doi":"10.1109/IPFA55383.2022.9915709","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915709","url":null,"abstract":"An intentionally overstressed fin defect was created in 5 nm technology. EBIC analysis with 0.5 kV electron beam stimulation enabled early detection of the defect during overstress experiments. EBIRCH analysis, again at 0.5 kV was able to isolate the exact spot of the fail in a multi-fin device. Additional EBIC scans at various kVs were also able to isolate the failing fin, located close to the EBIRCH spot, and provided insights on how to use Monte Carlo scattering models to predict the optimal beam energy to find defects via EBIC. This approach could be applied to fails in 5 nm or systems with delicate structures.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134378139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915756
A. Gu, M. Terada, H. Stegmann, Thomas Rodgers, C. Fu, Yanjing Yang
Non-destructive 3D X-ray microscopy (XRM) has played a crucial role in fueling the advances of IC package development and failure analysis [1]-[2]. Over the past decade, the industry has increasingly focused on packaging innovations to improve device performance. The emergence of numerous new 2.5D, 3D and recent heterogenous integration packages challenges the existing X-ray imaging and analysis techniques because IC interconnects are more densely packed in larger and thicker packages. It takes several hours or longer for a 3D X-ray scanner to acquire high resolution and quality images of fine-pitch interconnects and fault regions. In this report, we will introduce a deep learning high-resolution reconstruction (DLHRR) method through the implementation of trained neutral networks capable of improving scan speed by a factor of four. To demonstrate the effectiveness of this new method applied to the packaging hierarchy, an intact smartphone, several component modules, and embedded interconnectors will be imaged and reconstructed with the DLHRR method. With the improved efficiency of the AI powered X-ray imaging technique, a correlated fs-laser/FIB-SEM workflow followed to precisely target and analyze the deeply buried defects, which has been difficult, if not impossible, for conventional package FA techniques. We will discuss the DLHRR method and applications in two following workflows: X-ray imaging workflow for package structural analysis, and correlative X-ray and fs-laser/FIB-SEM workflow for package failure analysis.
{"title":"From System to Package to Interconnect: An Artificial Intelligence Powered 3D X-ray Imaging Solution for Semiconductor Package Structural Analysis and Correlative Microscopic Failure Analysis","authors":"A. Gu, M. Terada, H. Stegmann, Thomas Rodgers, C. Fu, Yanjing Yang","doi":"10.1109/IPFA55383.2022.9915756","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915756","url":null,"abstract":"Non-destructive 3D X-ray microscopy (XRM) has played a crucial role in fueling the advances of IC package development and failure analysis [1]-[2]. Over the past decade, the industry has increasingly focused on packaging innovations to improve device performance. The emergence of numerous new 2.5D, 3D and recent heterogenous integration packages challenges the existing X-ray imaging and analysis techniques because IC interconnects are more densely packed in larger and thicker packages. It takes several hours or longer for a 3D X-ray scanner to acquire high resolution and quality images of fine-pitch interconnects and fault regions. In this report, we will introduce a deep learning high-resolution reconstruction (DLHRR) method through the implementation of trained neutral networks capable of improving scan speed by a factor of four. To demonstrate the effectiveness of this new method applied to the packaging hierarchy, an intact smartphone, several component modules, and embedded interconnectors will be imaged and reconstructed with the DLHRR method. With the improved efficiency of the AI powered X-ray imaging technique, a correlated fs-laser/FIB-SEM workflow followed to precisely target and analyze the deeply buried defects, which has been difficult, if not impossible, for conventional package FA techniques. We will discuss the DLHRR method and applications in two following workflows: X-ray imaging workflow for package structural analysis, and correlative X-ray and fs-laser/FIB-SEM workflow for package failure analysis.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116149085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915780
Jayant D'Souza
Scan chains form a critical part of the test structures on digital designs. Chain diagnosis is commonly used in early yield ramp to root cause process issues. Recent advancements in chain diagnosis can not only improve chain diagnosis resolution but also provide more directed and meaningful information for failure analysis and fault isolation. This paper covers the basics of chain diagnosis and some recent technology advancements in chain diagnosis that have been leveraged in advanced process nodes below 7nm.
{"title":"Chain diagnosis as a tool for yield ramp in advanced process nodes","authors":"Jayant D'Souza","doi":"10.1109/IPFA55383.2022.9915780","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915780","url":null,"abstract":"Scan chains form a critical part of the test structures on digital designs. Chain diagnosis is commonly used in early yield ramp to root cause process issues. Recent advancements in chain diagnosis can not only improve chain diagnosis resolution but also provide more directed and meaningful information for failure analysis and fault isolation. This paper covers the basics of chain diagnosis and some recent technology advancements in chain diagnosis that have been leveraged in advanced process nodes below 7nm.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127220034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915767
C. Luo, Chaolun Wang, Shuo Ma, F. Liang, Zeiwei Luo, Xing Wu, J. Chu
Reliability of flexible device under external strain is an important issue. The clarification of complex evolution of structure under external strain is critical for basic physical understanding and reliability improvement. However, lack of the direction of the evolution process and the construction of the relationship between structure and electrical properties, the failure mechanism of flexible device remains controversial. Here, in situ transmission electron microscope (TEM) is used to directly observe the structural evolution during stretching and compression process in MoS2 based strain sensor. Through the analysis of the relationship between electrical properties and structure, the interfacial structure related gradual and abrupt resistance changes are observed. The formation of twisted and defected MoS2 layers during stretching process is important. The formed twisted MoS2 layers changes the current path, the resistance changes continuously. Then, the MoS2 is mechanically peeled off into two separate individuals, and the twisted MoS2 at the interface is removed in situ. By controlling the distance between two separate MoS2, the current has a sudden change. The in situ electrical TEM experiment clarified the relationship between the current (resistance) and the interface structure. It provides the experimental basis for the understanding of complex evolution mechanism under external strain, which is important for reliability of flexible device.
{"title":"In situ transmission electron microscope study of reliability in molybdenum disulfide based strain sensors","authors":"C. Luo, Chaolun Wang, Shuo Ma, F. Liang, Zeiwei Luo, Xing Wu, J. Chu","doi":"10.1109/IPFA55383.2022.9915767","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915767","url":null,"abstract":"Reliability of flexible device under external strain is an important issue. The clarification of complex evolution of structure under external strain is critical for basic physical understanding and reliability improvement. However, lack of the direction of the evolution process and the construction of the relationship between structure and electrical properties, the failure mechanism of flexible device remains controversial. Here, in situ transmission electron microscope (TEM) is used to directly observe the structural evolution during stretching and compression process in MoS2 based strain sensor. Through the analysis of the relationship between electrical properties and structure, the interfacial structure related gradual and abrupt resistance changes are observed. The formation of twisted and defected MoS2 layers during stretching process is important. The formed twisted MoS2 layers changes the current path, the resistance changes continuously. Then, the MoS2 is mechanically peeled off into two separate individuals, and the twisted MoS2 at the interface is removed in situ. By controlling the distance between two separate MoS2, the current has a sudden change. The in situ electrical TEM experiment clarified the relationship between the current (resistance) and the interface structure. It provides the experimental basis for the understanding of complex evolution mechanism under external strain, which is important for reliability of flexible device.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915733
W. Hubbard, J. Lodico, H. Chan, M. Mecklenburg, B. Regan
Dielectric breakdown (DB) is central to the failure and function of modern and next-generation computing components. Despite its importance in microelectronics, the specific mechanisms leading to DB are poorly understood. Electrical testing provides little spatial information about the small-scale effects that precede breakdown. High resolution imaging techniques, such as transmission electron microscopy (TEM), have the requisite resolution but are almost exclusively used to study the post-mortem effects of catastrophic DB. In this study we present techniques to directly visualize DB in nanoscale devices with scanning TEM electron beam-induced current (STEM EBIC) imaging. STEM EBIC imaging maps local conductivity and electric field with high contrast. In HfO2-based resistive memory (RRAM) devices, a data bit is stored as a conductive path formed via controlled, reversible DB. With STEM EBIC we image Ti/HfO2/Pt devices capable of switching repeatedly in situ. Distinct regions of soft and hard dielectric breakdown are observed at different phases of RRAM cycling. These results suggest a model where DB occurs on a progressive continuum between hard and soft breakdown.
{"title":"Nanoscale Conductivity Mapping: Live Imaging of Dielectric Breakdown with STEM EBIC","authors":"W. Hubbard, J. Lodico, H. Chan, M. Mecklenburg, B. Regan","doi":"10.1109/IPFA55383.2022.9915733","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915733","url":null,"abstract":"Dielectric breakdown (DB) is central to the failure and function of modern and next-generation computing components. Despite its importance in microelectronics, the specific mechanisms leading to DB are poorly understood. Electrical testing provides little spatial information about the small-scale effects that precede breakdown. High resolution imaging techniques, such as transmission electron microscopy (TEM), have the requisite resolution but are almost exclusively used to study the post-mortem effects of catastrophic DB. In this study we present techniques to directly visualize DB in nanoscale devices with scanning TEM electron beam-induced current (STEM EBIC) imaging. STEM EBIC imaging maps local conductivity and electric field with high contrast. In HfO2-based resistive memory (RRAM) devices, a data bit is stored as a conductive path formed via controlled, reversible DB. With STEM EBIC we image Ti/HfO2/Pt devices capable of switching repeatedly in situ. Distinct regions of soft and hard dielectric breakdown are observed at different phases of RRAM cycling. These results suggest a model where DB occurs on a progressive continuum between hard and soft breakdown.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127188512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-18DOI: 10.1109/IPFA55383.2022.9915752
Jungho Jin, Youngbong Han, Byung-Il Kown, Iloh Jang, N. Lee, Seungbae Lee, Yuchul Hwang, Hoosung Kim, S. Pae
Component-level charged device model (CDM) test method compliant with JS-002 is a good method to represent electro static discharge (ESD) failures of semiconductors. The CDM test method is useful to represent the ESD immunity of components constituting the system. However, there are factors that affect ESD immunity besides components in the system, it is important to verify ESD immunity in the system-level. In this paper, board-level CDM test method for solid state drives (SSDs) was proposed. This method can be used as a complementary method for system-level ESD test. A test environment suitable for SSD was set up using component-level CDM test equipment to reproduce ESD failure during assembly and test processes. The root-cause of the ESD failure is CDM damage caused by fast charge transfer between SSDs and adjacent objects. When SSD is combined with the equipment for electrical test, rapid charge transfer occurs through the metallic part of the SSD. A momentary voltage rise occurs at a specific node of semiconductors in SSD, and failure can be occurred. A failure of SSDs in assembly and test line was effectively replicated and root-cause identified and fixed.
{"title":"Investigation on Board-Level CDM in SSD Products and Replication of Line ESD Phenomena","authors":"Jungho Jin, Youngbong Han, Byung-Il Kown, Iloh Jang, N. Lee, Seungbae Lee, Yuchul Hwang, Hoosung Kim, S. Pae","doi":"10.1109/IPFA55383.2022.9915752","DOIUrl":"https://doi.org/10.1109/IPFA55383.2022.9915752","url":null,"abstract":"Component-level charged device model (CDM) test method compliant with JS-002 is a good method to represent electro static discharge (ESD) failures of semiconductors. The CDM test method is useful to represent the ESD immunity of components constituting the system. However, there are factors that affect ESD immunity besides components in the system, it is important to verify ESD immunity in the system-level. In this paper, board-level CDM test method for solid state drives (SSDs) was proposed. This method can be used as a complementary method for system-level ESD test. A test environment suitable for SSD was set up using component-level CDM test equipment to reproduce ESD failure during assembly and test processes. The root-cause of the ESD failure is CDM damage caused by fast charge transfer between SSDs and adjacent objects. When SSD is combined with the equipment for electrical test, rapid charge transfer occurs through the metallic part of the SSD. A momentary voltage rise occurs at a specific node of semiconductors in SSD, and failure can be occurred. A failure of SSDs in assembly and test line was effectively replicated and root-cause identified and fixed.","PeriodicalId":378702,"journal":{"name":"2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126611511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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