Timing optimization for testable convergent tree adders

Abstract

Carry lookahead adders have been, over the years, an integral part of microprocessor architecture. Structures and levels of adders vary depending on the carry output. In this paper, analysis and optimization processes are first performed on a testable convergent tree adder. It is shown that the structure of the tree provides for a high fanout with an imbalanced tree structure which contributes to a racing effect and increases the timing delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder the optimization in 1.2 /spl mu/m CMOS produces a 6.37% increase in speed of the critical path while only losing 2.16% in area. The full testability of the circuit is maintained in the optimized adder design.