Clock gating assertion check: An approach towards achieving faster verification closure on clock gating functionality

Abstract

Clock gating is a power reduction technique widely used in Register Transfer Level (RTL) stage of a chip design. The addition of clock gating logics has increased the complexity of a design and therefore requires considerable amount of verification effort. Furthermore, the scoreboard checking mechanism in Open Verification Methodology (OVM) verification environment still lacks the capability to completely comprehend the checking of clock gating logics correctness. To address this, a verification method, called Clock Gating Assertion Check (CGAC) method, independent of verification environment is proposed aiming at achieving a faster pre-silicon verification closure on clock gating logics with minimum verification effort. The proposed method is an automated flow using codes written in Hardware Description Language (HDL) in RTL stage and clock domains information of a design as the main inputs to generate checks at possible clock gating boundary conditions. The CGAC method was used to verify the clock gating logics of an existing Soft Intellectual Property (SIP) design. The implementation details of the method are discussed in this paper. By using the method, a total of 4 clock gating bugs were found and analysis on the impacts of the bugs is discussed. As a conclusion, the proposed method is proven effective in ensuring the correct clock gating implementation in a design.