Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274023
P. Roy, Mriganka Chakraborty, Aatreyi Bal, H. Rahaman, P. Dasgupta
Digital Microfluidic Biochips, a promising platform for Lab-on-chip systems are capable of automated biochemical analysis targeted for medical diagnostics and other biochemical applications. Due to its reconfigurability and scalability, a DMFB device is capable of integrating multiple bioassay protocols within the same array for simultaneous execution. We propose a DMFB design capable of executing multiple Bioassays selectively based on prior detection of results of already executed protocols at previous timestamps. We propose specified detection analyzers to be integrated with photodiodes preplaced at dedicated detection sites and a centralized memory to decide on the predefined signal set for a given execution sequence. The simulation is carried out using FPGA prototypes integrated with a DMFB with a prespecified layout for multilevel execution and the results are found to be in conformance with conventional benchtop procedures.
{"title":"Decision-based Biochips: A novel design for concurrent execution of networked bioassays integrated in scalable DMFBs","authors":"P. Roy, Mriganka Chakraborty, Aatreyi Bal, H. Rahaman, P. Dasgupta","doi":"10.1109/ACQED.2015.7274023","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274023","url":null,"abstract":"Digital Microfluidic Biochips, a promising platform for Lab-on-chip systems are capable of automated biochemical analysis targeted for medical diagnostics and other biochemical applications. Due to its reconfigurability and scalability, a DMFB device is capable of integrating multiple bioassay protocols within the same array for simultaneous execution. We propose a DMFB design capable of executing multiple Bioassays selectively based on prior detection of results of already executed protocols at previous timestamps. We propose specified detection analyzers to be integrated with photodiodes preplaced at dedicated detection sites and a centralized memory to decide on the predefined signal set for a given execution sequence. The simulation is carried out using FPGA prototypes integrated with a DMFB with a prespecified layout for multilevel execution and the results are found to be in conformance with conventional benchtop procedures.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116951022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274025
T. A. Anusudha, S. Prabaharan
Modern memories are very power hungry, larger in size, low retention period, low chip density and high cost. Memristor is a missing passive circuit element and regarded as a new class of emerging non-volatile memories overcoming the above problems. Memristor may be thought of an active as well as passive device based on the conditions of Memristance and Dynamic Negative Differential Resistance (DNDR). Memristor has been used for non-volatile memory applications, if and only if it produces non-linear pinched hysteresis curve. If the size of the pinched hysteresis curve increases, power dissipation increases as well. In this paper, we discuss the parametric analysis of memristor adopting the linear ion-drift model to achieve low power dissipation while retaining the nonlinear i-v characteristics.
{"title":"Realization of non-linear i-v curve with low power dissipation using linear ion drift memristor model","authors":"T. A. Anusudha, S. Prabaharan","doi":"10.1109/ACQED.2015.7274025","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274025","url":null,"abstract":"Modern memories are very power hungry, larger in size, low retention period, low chip density and high cost. Memristor is a missing passive circuit element and regarded as a new class of emerging non-volatile memories overcoming the above problems. Memristor may be thought of an active as well as passive device based on the conditions of Memristance and Dynamic Negative Differential Resistance (DNDR). Memristor has been used for non-volatile memory applications, if and only if it produces non-linear pinched hysteresis curve. If the size of the pinched hysteresis curve increases, power dissipation increases as well. In this paper, we discuss the parametric analysis of memristor adopting the linear ion-drift model to achieve low power dissipation while retaining the nonlinear i-v characteristics.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117178965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274009
C. Kuan, Jimmy Huang, B. E. Cheah, J. Kong
Maximum current (Imax) distribution across substrate has been one of the major design factors that govern the electronic package form factor. Particularly on ball grid array (BGA) package design, often times Imax distribution determines the number of solder balls required for each interface to sustain respective workloads hence defines the total ball count and the x-y dimension of the electronic package. This paper introduces a new method to improve BGA Imax distribution while keeping ball count minimal for to enable small form-factor package design. The proposed solution utilizes fundamental of electrical resistance control through on-board BGA pad design customization to achieve more uniform Imax distribution across solder balls and enable up-to 25% Imax reduction with negligible IR drop impact. Power losses across plane were also simulated and compared against conventional design in this study.
{"title":"Method to improve ball grid array Imax distribution for small form factor package design","authors":"C. Kuan, Jimmy Huang, B. E. Cheah, J. Kong","doi":"10.1109/ACQED.2015.7274009","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274009","url":null,"abstract":"Maximum current (Imax) distribution across substrate has been one of the major design factors that govern the electronic package form factor. Particularly on ball grid array (BGA) package design, often times Imax distribution determines the number of solder balls required for each interface to sustain respective workloads hence defines the total ball count and the x-y dimension of the electronic package. This paper introduces a new method to improve BGA Imax distribution while keeping ball count minimal for to enable small form-factor package design. The proposed solution utilizes fundamental of electrical resistance control through on-board BGA pad design customization to achieve more uniform Imax distribution across solder balls and enable up-to 25% Imax reduction with negligible IR drop impact. Power losses across plane were also simulated and compared against conventional design in this study.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"20 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125775153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274002
Pavan Vithal Torvi, V. Devanathan, Ashish Vanjari, V. Kamakoti
The advancement in the semiconductor manufacturing process has reduced the device dimensions, which in turn has reduced design and manufacturing costs of the Integrated Chips (IC). This has accelerated the IC penetration in automobiles, health care and safety critical systems. However, the smaller device dimensions have made the ICs vulnerable to soft-errors. The sequential cells in a given design contribute significantly to its soft-error rate (SER). Some of the soft-errors get masked and do not cause any adverse impact. The masking can occur due to logic or timing reasons. This paper presents a flow that uses the Timing Vulnerability Factor (TVF) and Architecture Vulnerability Factor (AVF) of the sequential instances in a given design to reduce its soft-error rate (SER). The paper proposes a novel method to efficiently compute the TVF and AVF parameters followed by a linear programming technique that uses these parameters to reduce the SER of the given design. Using the proposed technique, we have reduced the sequential cell contribution to the SER of an in-house IP design by 36% for an increase of 9% in sequential cells area.
{"title":"SER mitigation technique through selective flip-flop replacement","authors":"Pavan Vithal Torvi, V. Devanathan, Ashish Vanjari, V. Kamakoti","doi":"10.1109/ACQED.2015.7274002","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274002","url":null,"abstract":"The advancement in the semiconductor manufacturing process has reduced the device dimensions, which in turn has reduced design and manufacturing costs of the Integrated Chips (IC). This has accelerated the IC penetration in automobiles, health care and safety critical systems. However, the smaller device dimensions have made the ICs vulnerable to soft-errors. The sequential cells in a given design contribute significantly to its soft-error rate (SER). Some of the soft-errors get masked and do not cause any adverse impact. The masking can occur due to logic or timing reasons. This paper presents a flow that uses the Timing Vulnerability Factor (TVF) and Architecture Vulnerability Factor (AVF) of the sequential instances in a given design to reduce its soft-error rate (SER). The paper proposes a novel method to efficiently compute the TVF and AVF parameters followed by a linear programming technique that uses these parameters to reduce the SER of the given design. Using the proposed technique, we have reduced the sequential cell contribution to the SER of an in-house IP design by 36% for an increase of 9% in sequential cells area.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123255375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274020
K. Yeap, Jor Gie Liew, S. Loh, H. Nisar, Z. I. Rizman
We present the design and analysis of 22 nm deep submicron indium gallium nitride InGaN and silicon Si NMOS transistors. The results show that the saturation and breakdown behavior of the InGaN transistor is significantly higher than that of its silicon Si counterpart. Our analysis suggests that InGaN could be a better alternative substrate material in the design and fabrication of transistors, as the size of the channel approaches the mean free path of the carriers.
{"title":"Performance analysis of 22 nm deep submicron NMOS transistors","authors":"K. Yeap, Jor Gie Liew, S. Loh, H. Nisar, Z. I. Rizman","doi":"10.1109/ACQED.2015.7274020","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274020","url":null,"abstract":"We present the design and analysis of 22 nm deep submicron indium gallium nitride InGaN and silicon Si NMOS transistors. The results show that the saturation and breakdown behavior of the InGaN transistor is significantly higher than that of its silicon Si counterpart. Our analysis suggests that InGaN could be a better alternative substrate material in the design and fabrication of transistors, as the size of the channel approaches the mean free path of the carriers.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128011126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274000
V. Pangracious, Z. Marrakchi, H. Mehrez
In this paper we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for FPGA architecture design. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, a 2.5D or 3D high density MoT FPGAs can be designed. To design 3D multi-stacked MoT-based FPGAs, the 2D MoT FPGA is cut into two or more equal sections by adjusting the long wire span. The long wire segments are realized using 3D through silicon via (TSV). To design 2.5D interposer-based multi-FPGAs, we increase the number of cuts and apply appropriate optimization models to scale down the number of long wires and horizontal inter-FPGA interposer wires. Using our 2.5/3D design and simulation CAD flow, we demonstrate the speed and area of 3D MoT-based FPGA architecture is improved by 54% and 41% respectively in comparison to 3D Mesh-based FPGA.
在本文中，我们提出了一种基于改进的树网格(MoT)拓扑的三维(3D)互连网络实现，用于FPGA架构设计。为了获得最佳的mot互连结构，修改了二维mot FPGA的路由架构，使其包含跨越每行和每列多个交换块的长路由段。通过调整长导线和跨距的比例，可以设计出2.5D或3D高密度MoT fpga。为了设计3D多堆叠MoT FPGA，通过调整长线跨度将2D MoT FPGA切割成两个或多个相等的部分。长线段采用三维硅通孔(TSV)技术实现。为了设计基于2.5D中间层的多fpga，我们增加了切割数量，并应用适当的优化模型来减少长线和水平fpga间中间层线的数量。利用我们的2.5/3D设计和仿真CAD流程，我们证明了基于3D mot的FPGA架构的速度和面积分别比基于3D mesh的FPGA提高了54%和41%。
{"title":"An efficient Mesh-of-Tree based interconnect architecture for high performance 3D FPGAs","authors":"V. Pangracious, Z. Marrakchi, H. Mehrez","doi":"10.1109/ACQED.2015.7274000","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274000","url":null,"abstract":"In this paper we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Trees (MoT) topology for FPGA architecture design. To obtain the optimal MoT-based interconnect structure, the routing architecture of the 2D MoT-based FPGA is modified to include long routing segments that span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, a 2.5D or 3D high density MoT FPGAs can be designed. To design 3D multi-stacked MoT-based FPGAs, the 2D MoT FPGA is cut into two or more equal sections by adjusting the long wire span. The long wire segments are realized using 3D through silicon via (TSV). To design 2.5D interposer-based multi-FPGAs, we increase the number of cuts and apply appropriate optimization models to scale down the number of long wires and horizontal inter-FPGA interposer wires. Using our 2.5/3D design and simulation CAD flow, we demonstrate the speed and area of 3D MoT-based FPGA architecture is improved by 54% and 41% respectively in comparison to 3D Mesh-based FPGA.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126239327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7273998
Farah B. Yahya, H. Patel, V. Chandra, B. Calhoun
This paper investigates the use of combined read and write assist techniques to reduce the minimum operating voltage (VMIN) of the 6T SRAM bit-cell. While write failures initially limit VMIN, applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling VMIN down to near/sub threshold voltages. We find that combining negative bitline (BL) for write assist with array VDD boosting for read assist is most effective for reducing the array VMIN and eliminating half-select failures for commercial 130nm and sub-20nm FinFET technologies across different process corners and temperatures. The proposed combination results in the highest reduction in SRAM VMIN (to 300mV for FinFET and to 600mV for 130nm CMOS). This paper also shows that controlling the degree of applied assist based on the chip corner will allow further reductions in VMIN for the 130nm CMOS (to 450mV) and the required assist needed to achieve VMIN for both the FinFET and the 130nm bit-cells.
{"title":"Combined SRAM read/write assist techniques for near/sub-threshold voltage operation","authors":"Farah B. Yahya, H. Patel, V. Chandra, B. Calhoun","doi":"10.1109/ACQED.2015.7273998","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7273998","url":null,"abstract":"This paper investigates the use of combined read and write assist techniques to reduce the minimum operating voltage (VMIN) of the 6T SRAM bit-cell. While write failures initially limit VMIN, applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling VMIN down to near/sub threshold voltages. We find that combining negative bitline (BL) for write assist with array VDD boosting for read assist is most effective for reducing the array VMIN and eliminating half-select failures for commercial 130nm and sub-20nm FinFET technologies across different process corners and temperatures. The proposed combination results in the highest reduction in SRAM VMIN (to 300mV for FinFET and to 600mV for 130nm CMOS). This paper also shows that controlling the degree of applied assist based on the chip corner will allow further reductions in VMIN for the 130nm CMOS (to 450mV) and the required assist needed to achieve VMIN for both the FinFET and the 130nm bit-cells.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127276132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274016
S. Arasu, M. Nourani, Hao Luo
In this paper, we analyze the impact of asymmetrical aging due to Bias Temperature Instability (BTI) in the clock tree segments of power efficient designs. The nonuniform aging of launch and capture clock segments could not only violate the setup timing but also result in gross hold violations. Aging in clock networks also results in pulse width compression which impacts the half-cycle paths' timing adversely. We present a reference-less alldigital technique to detect the aging effects and measure quantitatively the extent of pulse-width-distortion. The measurement results are then applied to rectify the pulse width distortion such that the clock network output is restored to a 50-50 duty cycle. The technique is validated using SPICE simulation based on 45nm industry standard library. A resolution of sub-1ps is achievable for both distortion measurement and correction circuits.
{"title":"An all-digital adaptive approach to combat aging effects in clock networks","authors":"S. Arasu, M. Nourani, Hao Luo","doi":"10.1109/ACQED.2015.7274016","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274016","url":null,"abstract":"In this paper, we analyze the impact of asymmetrical aging due to Bias Temperature Instability (BTI) in the clock tree segments of power efficient designs. The nonuniform aging of launch and capture clock segments could not only violate the setup timing but also result in gross hold violations. Aging in clock networks also results in pulse width compression which impacts the half-cycle paths' timing adversely. We present a reference-less alldigital technique to detect the aging effects and measure quantitatively the extent of pulse-width-distortion. The measurement results are then applied to rectify the pulse width distortion such that the clock network output is restored to a 50-50 duty cycle. The technique is validated using SPICE simulation based on 45nm industry standard library. A resolution of sub-1ps is achievable for both distortion measurement and correction circuits.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127729039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274012
Y. Zhang, Bin Wang, Haipeng Zhang, Weixin Kong
This paper presented a new kind of Omni-directional UHF RFID tag antenna. The antenna is composed of four identical arrow-shape modules that are completely center-symmetric. Compared with the traditional dipole planar antenna, the antenna proposed has a -10dB bandwidth at 244MHz and shows better performance in Omni-direction in the reading range. The new Omni-directional UHF RFID tag antenna can effectively eliminate the reading blind spots caused by the antenna direction.
{"title":"True 3D antenna for UHF RFID application","authors":"Y. Zhang, Bin Wang, Haipeng Zhang, Weixin Kong","doi":"10.1109/ACQED.2015.7274012","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274012","url":null,"abstract":"This paper presented a new kind of Omni-directional UHF RFID tag antenna. The antenna is composed of four identical arrow-shape modules that are completely center-symmetric. Compared with the traditional dipole planar antenna, the antenna proposed has a -10dB bandwidth at 244MHz and shows better performance in Omni-direction in the reading range. The new Omni-directional UHF RFID tag antenna can effectively eliminate the reading blind spots caused by the antenna direction.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128682778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274001
N. Wary, P. Mandal
A new current-mode simultaneous bidirectional transceiver for high speed asynchronous communication over on-chip global interconnects has been proposed in this paper. The new transceiver can receive and transmit the data simultaneously over a same differential interconnect, thereby decreasing the number of interconnects required compared to unidirectional signalling schemes. The transceiver provides a low input impedance and so supports high bandwidth of transmission. The circuit has been implemented in 65nm UMC process with a global interconnect of length 5mm and width 1.5μm. The energy efficiency of the transceiver for simultaneous bidirectional data transmission of 10 Gbps data is 0.38 pJ/b.
{"title":"Current-mode simultaneous bidirectional transceiver for on-chip global interconnects","authors":"N. Wary, P. Mandal","doi":"10.1109/ACQED.2015.7274001","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274001","url":null,"abstract":"A new current-mode simultaneous bidirectional transceiver for high speed asynchronous communication over on-chip global interconnects has been proposed in this paper. The new transceiver can receive and transmit the data simultaneously over a same differential interconnect, thereby decreasing the number of interconnects required compared to unidirectional signalling schemes. The transceiver provides a low input impedance and so supports high bandwidth of transmission. The circuit has been implemented in 65nm UMC process with a global interconnect of length 5mm and width 1.5μm. The energy efficiency of the transceiver for simultaneous bidirectional data transmission of 10 Gbps data is 0.38 pJ/b.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125440180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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