Real-time digital predistortion for radio frequency power amplifier linearization

S. Ferguson, A. Chopra
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引用次数: 3

Abstract

In this paper, a system is proposed for real-time calculation of digital predistortion (DPD) coefficients to linearize wideband radio frequency (RF) power amplifiers (PAs). The proposed system leverages the commercially available National Instruments (NI) PXIe-5646R vector signal transceiver (VST) platform. The VST is a single module RF instrument that combines a 200MHz instantaneous vector signal analyzer (VSA) and vector signal generator (VSG) with a shared Xilinx LX240T field-programmable gate array (FPGA). The FPGA is used to perform look-up table (LUT) predistorter estimation and predistortion in real-time. The proposed system is shown to reduce the time to generate a predistorted waveform by over two orders of magnitude compared to a software implementation. Furthermore, the linearity achieved with the proposed FPGA implementation closely matches a traditional software-based approach, with 15dB improvement in adjacent channel leakage ratio (ACLR) and a 3x improvement in error vector magnitude (EVM) for a 3G mobile handset power amplifier.
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射频功率放大器线性化的实时数字预失真
本文提出了一种实时计算数字预失真(DPD)系数的系统,用于线性化宽带射频功率放大器(pa)。该系统采用美国国家仪器公司(NI)的PXIe-5646R矢量信号收发器(VST)平台。VST是一种单模块射频仪器,结合了200MHz瞬时矢量信号分析仪(VSA)和矢量信号发生器(VSG)以及共享的Xilinx LX240T现场可编程门阵列(FPGA)。该FPGA用于实时执行查找表预失真估计和预失真。与软件实现相比,所提出的系统可以将产生预失真波形的时间减少两个数量级以上。此外,所提出的FPGA实现实现的线性度与传统的基于软件的方法非常接近,相邻通道泄漏比(ACLR)提高了15dB,误差矢量幅度(EVM)提高了3倍,用于3G手机功率放大器。
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