{"title":"Analyzing BIST robustness","authors":"J. Sosnowski","doi":"10.1109/DFTVS.2001.966758","DOIUrl":null,"url":null,"abstract":"Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account. Moreover we check fault impact on software procedures related to BIST and error handling mechanisms using software implemented fault injector.","PeriodicalId":187031,"journal":{"name":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.2001.966758","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Deals with the problem of fault detection and fault handling robustness in BIST schemes. In particular we analyze the susceptibility of signature analyzers to internal faults. Various fault models (black box) within the analyzer circuitry are taken into account. Moreover we check fault impact on software procedures related to BIST and error handling mechanisms using software implemented fault injector.
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