Predictive tools in VLSI system design: timing aspects

Abstract

A major problem in hierarchical design is to achieve consistency of the design steps that will not require iterations and will converge to the 'reasonably good' solution. To achieve this goal, additional efforts need to be made of each level of the hierarchical top-down process to derive constraints on variables of the lower level of hierarchy and use these additional constraints to solve the problems of lower levels. The authors illustrate this concept with the design step positioned between the logical level of simulation for VLSI and the physical implementation of the design. This step performs the timing analysis of the logic and provides constraints for the physical implementation of the design. If these constraints are satisfied on the layout phase, then timing-error-free design is obtained.<>