A Source and Drain Transient Currents Technique for Trap Characterisation in AIGaN/GaN HEMTs

Abstract

The source/drain and gate induced charge trapping within an AIGaN/GaN high electron mobility transistor is studied, under normal device operation, by excluding self-heating effects, for the first time. Through direct measurement of current transients of both source and drain terminals, a characterisation technique has been developed to: (i) analyse the transient current degradations from μS to seconds, and (ii) evaluate the drain and gate induced charge trapping mechanisms. Two degradation mechanisms of current are observed: bulk trapping at a short time <1ms); and surface trapping and redistribution (>lms). The bulk charge trapping is found to occur during both ON and OFF states of the device when Vns>0V; where its trapping time constant is independent of bias conditions. In addition, the time constant of the slower current degradation is found to be mainly dependent on surface trapping and redistribution, not by the second heat transient.