S. Chetlur, J. Zaneski, L. Mullin, A. Oates, R. Ashton, H. Chew, J. Zhou
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引用次数: 0
Abstract
Self-stressing testers are used to study the impact of input voltage swing on the aging behavior of 0.18 NMOS devices in inverters. When the frequency and rise/fall time of the input pulse are altered, we demonstrate that the effective aging time 't/sub eff/' per clock cycle varies with the rise/fall transitions and is the main factor in deciding NMOS degradation.
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