Pub Date : 2000-03-16DOI: 10.1109/ICMTS.2000.1193989
R. Gillon, W. Van De Sype, D. Vanhoenaker, L. Martens
A comparison is made between the widely used immittance correction technique (dummy dc-embedding) and the newel" in-situ calibration. The accuracy of the immittancc CDITcClion technique is limited hy the ils$llmption that the rcl"crcnce structures lHve ideal characteristics. Using ill-situ cal ilmltlon tlic true characteristics of these structures call be me
{"title":"Comparing high-frequency de-embedding strategies: immittance correction and in-situ calibration","authors":"R. Gillon, W. Van De Sype, D. Vanhoenaker, L. Martens","doi":"10.1109/ICMTS.2000.1193989","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.1193989","url":null,"abstract":"A comparison is made between the widely used immittance correction technique (dummy dc-embedding) and the newel\" in-situ calibration. The accuracy of the immittancc CDITcClion technique is limited hy the ils$llmption that the rcl\"crcnce structures lHve ideal characteristics. Using ill-situ cal ilmltlon tlic true characteristics of these structures call be me<l�urcd so that the accuracy limitlltions of immittance !:olTeclions !:<In be assessed exactly. In-situ calibration appears to he inlwrcntly more aecuratc ,md flexible, especially on ]m;sy silicon substrates.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131470817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-16DOI: 10.1109/ICMTS.2000.844439
T. Kolding, O. Jensen, T. Larsen
This paper presents a new test fixture with associated de-embedding procedure for efficient and accurate on-wafer device measurements at microwave frequencies. The fixture is based on a substrate shield and (i) provides an accurate common ground for N-port measurements, (ii) effectively reduces substrate carried coupling, (iii) gives well-defined parasitics for simplified de-embedding, and (iv) fits arbitrarily large devices. Due to these characteristics, the accompanying de-embedding technique requires only few in-fixture standards that can be fabricated with very high accuracy; even in standard CMOS processes. The technique can advantageously be applied to a wide range of commonly used processes, but highest performance improvement is achieved with low-resistivity substrates. The performance of the technique is demonstrated to 12 GHz in a 0.25 /spl mu/m CMOS technology and conclusions are drawn.
本文提出了一种新的测试夹具及其相关的去嵌入程序，用于在微波频率下高效准确地测量片上器件。该夹具基于基板屏蔽，并且(i)为n端口测量提供了准确的公共接地，(ii)有效地减少了基板携带的耦合，(iii)为简化的去嵌入提供了明确的寄生，(iv)适合任意大的设备。由于这些特点，伴随的去嵌入技术只需要很少的夹具内标准，可以以非常高的精度制造;即使在标准的CMOS工艺中。该技术可以有利地应用于广泛的常用工艺，但最大的性能改进是在低电阻率衬底上实现的。在0.25 /spl μ m CMOS技术下，对该技术在12 GHz下的性能进行了验证，并得出了结论。
{"title":"Ground-shielded measuring technique for accurate on-wafer characterization of RF CMOS devices","authors":"T. Kolding, O. Jensen, T. Larsen","doi":"10.1109/ICMTS.2000.844439","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844439","url":null,"abstract":"This paper presents a new test fixture with associated de-embedding procedure for efficient and accurate on-wafer device measurements at microwave frequencies. The fixture is based on a substrate shield and (i) provides an accurate common ground for N-port measurements, (ii) effectively reduces substrate carried coupling, (iii) gives well-defined parasitics for simplified de-embedding, and (iv) fits arbitrarily large devices. Due to these characteristics, the accompanying de-embedding technique requires only few in-fixture standards that can be fabricated with very high accuracy; even in standard CMOS processes. The technique can advantageously be applied to a wide range of commonly used processes, but highest performance improvement is achieved with low-resistivity substrates. The performance of the technique is demonstrated to 12 GHz in a 0.25 /spl mu/m CMOS technology and conclusions are drawn.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123835316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-16DOI: 10.1109/ICMTS.2000.844418
P. Drennan, C. McAndrew, J. Bates, D. Schroder
This paper presents a new technique for the simple and rapid evaluation of the process and geometry parameter contributions to BJT mismatch. The pinched base sheet resistance variation, the geometric emitter size variation, and the ideal component of the emitter-base current variation can be uniquely determined from the I/sub c/, I/sub b/ and /spl beta/ mismatch variances in the ideal region. The variation in the nonideal component of the base current can be evaluated from the I/sub b/ and /spl beta/ mismatch in low level injection region. The variation in extrinsic resistance can be evaluated from the I/sub c/ and I/sub b/ mismatch in the high current region. The mismatch evaluation can be performed with as few as six measurements per device type per die site.
{"title":"Rapid evaluation of the root causes of BJT mismatch","authors":"P. Drennan, C. McAndrew, J. Bates, D. Schroder","doi":"10.1109/ICMTS.2000.844418","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844418","url":null,"abstract":"This paper presents a new technique for the simple and rapid evaluation of the process and geometry parameter contributions to BJT mismatch. The pinched base sheet resistance variation, the geometric emitter size variation, and the ideal component of the emitter-base current variation can be uniquely determined from the I/sub c/, I/sub b/ and /spl beta/ mismatch variances in the ideal region. The variation in the nonideal component of the base current can be evaluated from the I/sub b/ and /spl beta/ mismatch in low level injection region. The variation in extrinsic resistance can be evaluated from the I/sub c/ and I/sub b/ mismatch in the high current region. The mismatch evaluation can be performed with as few as six measurements per device type per die site.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"29 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114036107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-16DOI: 10.1109/ICMTS.2000.844427
E. Griffith, J. A. Power, S. C. Kelly, P. Elebert, S. Whiston, D. Bain, M. O’Neill
High voltage integrated circuits (HVIC's) are emerging as viable alternatives to discrete circuits in a wide variety of applications. A commonly used high voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). The LDMOS transistor is based on the lightly doped drain concept. Two of the main objectives in designing LDMOS devices are to minimize the on-resistance while still maintaining a high breakdown voltage. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the gate oxide and polysilicon beyond the channel into this region. This lightly doped drain region can have a large effect on the on-resistance, saturation current and feedback capacitance of the device. This paper presents a LDMOS device, considers some of the key specific parameters related to LDMOS devices, discusses a sub-circuit SPICE model implemented to model the LDMOS characteristics and investigates some interconnect metallization effects.
{"title":"Characterization and modeling of LDMOS transistors on a 0.6 /spl mu/m CMOS technology","authors":"E. Griffith, J. A. Power, S. C. Kelly, P. Elebert, S. Whiston, D. Bain, M. O’Neill","doi":"10.1109/ICMTS.2000.844427","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844427","url":null,"abstract":"High voltage integrated circuits (HVIC's) are emerging as viable alternatives to discrete circuits in a wide variety of applications. A commonly used high voltage component of these circuits is the lateral double diffused MOS transistor (LDMOS). The LDMOS transistor is based on the lightly doped drain concept. Two of the main objectives in designing LDMOS devices are to minimize the on-resistance while still maintaining a high breakdown voltage. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the gate oxide and polysilicon beyond the channel into this region. This lightly doped drain region can have a large effect on the on-resistance, saturation current and feedback capacitance of the device. This paper presents a LDMOS device, considers some of the key specific parameters related to LDMOS devices, discusses a sub-circuit SPICE model implemented to model the LDMOS characteristics and investigates some interconnect metallization effects.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130230732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844437
J. Carpentier, S. Gellida, D. Gloria, G. Morin, H. Jaouen
As the frequency increases for RF applications in silicon technology, the modeling of transmission lines is necessary. In this work, we propose to check the validity of the conventional measurement technique to extract the propagation parameters for structures in a standard BiCMOS process. To estimate this technique, the results are compared with 2D electromagnetic simulations. On microstrip structures, the comparison shows that the conventional method is sufficient up to 18 GHz. Moreover, we highlight the effects of energy dissipation in the dielectric layers currently used in the silicon process.
{"title":"Comparison between S-parameter measurements and 2D electromagnetic simulations for microstrip transmission lines on BiCMOS process","authors":"J. Carpentier, S. Gellida, D. Gloria, G. Morin, H. Jaouen","doi":"10.1109/ICMTS.2000.844437","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844437","url":null,"abstract":"As the frequency increases for RF applications in silicon technology, the modeling of transmission lines is necessary. In this work, we propose to check the validity of the conventional measurement technique to extract the propagation parameters for structures in a standard BiCMOS process. To estimate this technique, the results are compared with 2D electromagnetic simulations. On microstrip structures, the comparison shows that the conventional method is sufficient up to 18 GHz. Moreover, we highlight the effects of energy dissipation in the dielectric layers currently used in the silicon process.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116432267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844422
U. Schaper, C. Linnenbank, R. Thewes
A new test structure is presented for the characterization of long distance mismatch of CMOS devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for different CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices and examples for linear and nonlinear distance dependencies are shown.
{"title":"A novel approach for precise characterization of long distance mismatch of CMOS-devices","authors":"U. Schaper, C. Linnenbank, R. Thewes","doi":"10.1109/ICMTS.2000.844422","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844422","url":null,"abstract":"A new test structure is presented for the characterization of long distance mismatch of CMOS devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for different CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices and examples for linear and nonlinear distance dependencies are shown.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844430
J. Goto, S. Kuwabara, T. Tsujide
The recent development of high performance LSIs requires a lot of expensive and time-consuming measurements of device characteristics at the process development stages. This paper introduces a new test structure to measure device characteristics with drastically reduced run-time and chip-area overheads, and also shows the possibility of unifying function tests and device characteristic measurements.
{"title":"Embedded compact test structure with a comparator for rapid device characteristic measurement","authors":"J. Goto, S. Kuwabara, T. Tsujide","doi":"10.1109/ICMTS.2000.844430","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844430","url":null,"abstract":"The recent development of high performance LSIs requires a lot of expensive and time-consuming measurements of device characteristics at the process development stages. This paper introduces a new test structure to measure device characteristics with drastically reduced run-time and chip-area overheads, and also shows the possibility of unifying function tests and device characteristic measurements.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115863660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844417
Chunbo Liu, J. Ma, Jeongmin Choi
A test structure was designed to enable an electrical determination of gate length reduction due to micro-loading effects in poly. A transistor with parallel dummy poly's and transistors with isolated poly's were compared. We propose that DIBL effects be used to extract gate length reduction without being affected by any parasitic resistance in source/drain regions. The results agreed well with cross-section SEM analysis, and were confirmed by the measured and simulated speeds of NAND/NOR ring oscillator circuits.
{"title":"An electrical technique for determining MOSFET gate length reduction due to process micro-loading effects in advanced CMOS technology","authors":"Chunbo Liu, J. Ma, Jeongmin Choi","doi":"10.1109/ICMTS.2000.844417","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844417","url":null,"abstract":"A test structure was designed to enable an electrical determination of gate length reduction due to micro-loading effects in poly. A transistor with parallel dummy poly's and transistors with isolated poly's were compared. We propose that DIBL effects be used to extract gate length reduction without being affected by any parasitic resistance in source/drain regions. The results agreed well with cross-section SEM analysis, and were confirmed by the measured and simulated speeds of NAND/NOR ring oscillator circuits.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116361998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844434
F. Pio, E. Gomiero
A test structure consisting of a not addressable EEPROM cell array is presented together with the measurement methodology. Accurate information on the threshold voltage distribution of the cells in the array is obtained from the transfer characteristic measured under select transistor clamping bias. We discuss in detail the working principle and the different levels of approximation, presenting several results for early process/design reliability evaluation (bake retention, control gate stress, programming pulse optimisation).
{"title":"Select transistor modulated cell array structure test for EEPROM reliability","authors":"F. Pio, E. Gomiero","doi":"10.1109/ICMTS.2000.844434","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844434","url":null,"abstract":"A test structure consisting of a not addressable EEPROM cell array is presented together with the measurement methodology. Accurate information on the threshold voltage distribution of the cells in the array is obtained from the transfer characteristic measured under select transistor clamping bias. We discuss in detail the working principle and the different levels of approximation, presenting several results for early process/design reliability evaluation (bake retention, control gate stress, programming pulse optimisation).","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123541663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844394
M. Fallen, D. McAlpine
Electrical measurement of metal linewidths is generally more demanding than other layers produced in IC processing because of the low resistivity of the material. To enable accurate measurements to be made, an appreciable voltage must be generated. The trade off that arises is in size of test structure against the accuracy of the voltmeter. Presented here is a new structure and method of reconciling this tradeoff, allowing a level of process control without the overhead of a high resolution voltmeter or an unacceptable use of silicon real estate.
{"title":"A new test structure to measure metal linewidths using minimum real estate","authors":"M. Fallen, D. McAlpine","doi":"10.1109/ICMTS.2000.844394","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844394","url":null,"abstract":"Electrical measurement of metal linewidths is generally more demanding than other layers produced in IC processing because of the low resistivity of the material. To enable accurate measurements to be made, an appreciable voltage must be generated. The trade off that arises is in size of test structure against the accuracy of the voltmeter. Presented here is a new structure and method of reconciling this tradeoff, allowing a level of process control without the overhead of a high resolution voltmeter or an unacceptable use of silicon real estate.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123671974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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