{"title":"Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications","authors":"Miao Li, P. Noel, T. Kwasniewski, Shoujun Wang","doi":"10.1109/IWSOC.2005.48","DOIUrl":null,"url":null,"abstract":"Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-/spl mu/m CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation over a 34\" FR4 backplane.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"401 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2005.48","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-/spl mu/m CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation over a 34" FR4 backplane.
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