J. Ellis-Monaghan, Yun Shi, S. Sharma, N. Feilchenfeld, T. Letavic, R. Phelps, C. Hedges, D. Cook, J. Dunn
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引用次数: 1
Abstract
A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.
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