Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229039
Yong-Keon Choi, I. Park, H. Oh, Wook Lee, Nam-Joo Kim, K. Yoo
A 12V low Vgs (1.8V) RF-N/PLDMOS have been successfully implemented on the 0.18 μm analog CMOS process without thermal budget addition. N- and P-ch LDMOS needs additional body and drift implants, respectively. A short channel length and a small overlap of gate-to-drain were accomplished by the optimization of implant conditions for the source halo and the drift region which is followed by the gate formation with 30 Å gate oxide. Cut-off frequency 37.2GHz and 12.9GHz each for NLDMOS and PLDMOS were achieved with breakdown voltage of 20V. The long-term wafer level HCI test result showed Idlin shift under 10% after 150Ksec stress at Vds=12V and Vgs=1.8V.
{"title":"Implementation of low Vgs (1.8V) 12V RF-LDMOS for high-frequency DC-DC converter applications","authors":"Yong-Keon Choi, I. Park, H. Oh, Wook Lee, Nam-Joo Kim, K. Yoo","doi":"10.1109/ISPSD.2012.6229039","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229039","url":null,"abstract":"A 12V low Vgs (1.8V) RF-N/PLDMOS have been successfully implemented on the 0.18 μm analog CMOS process without thermal budget addition. N- and P-ch LDMOS needs additional body and drift implants, respectively. A short channel length and a small overlap of gate-to-drain were accomplished by the optimization of implant conditions for the source halo and the drift region which is followed by the gate formation with 30 Å gate oxide. Cut-off frequency 37.2GHz and 12.9GHz each for NLDMOS and PLDMOS were achieved with breakdown voltage of 20V. The long-term wafer level HCI test result showed Idlin shift under 10% after 150Ksec stress at Vds=12V and Vgs=1.8V.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125326445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229024
P. Hower, Ç. Kaya, S. Pendharkar, C. Jones
Failure during reverse recovery of an IC power diode is examined. It is shown how one-dimensional diode behavior together with mixed-mode tcad can be used to predict safe operating conditions for the actual two-dimensional case.
{"title":"Reverse-recovery safe operating area of diodes in power integrated circuits","authors":"P. Hower, Ç. Kaya, S. Pendharkar, C. Jones","doi":"10.1109/ISPSD.2012.6229024","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229024","url":null,"abstract":"Failure during reverse recovery of an IC power diode is examined. It is shown how one-dimensional diode behavior together with mixed-mode tcad can be used to predict safe operating conditions for the actual two-dimensional case.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229088
Zhenxian Liang
Comprehensive requirements in aspects of cost, reliability, efficiency, form factor, weight, and volume for power electronics modules in modern electric drive vehicles have driven the development of automotive power packaging technology intensively. Innovation in materials, interconnections, and processing techniques is leading to enormous improvements in power modules. In this paper, the technical development of and trends in power module packaging are evaluated by examining technical details with examples of industrial products. The issues and development directions for future automotive power module packaging are also discussed.
{"title":"Status and trend of automotive power packaging","authors":"Zhenxian Liang","doi":"10.1109/ISPSD.2012.6229088","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229088","url":null,"abstract":"Comprehensive requirements in aspects of cost, reliability, efficiency, form factor, weight, and volume for power electronics modules in modern electric drive vehicles have driven the development of automotive power packaging technology intensively. Innovation in materials, interconnections, and processing techniques is leading to enormous improvements in power modules. In this paper, the technical development of and trends in power module packaging are evaluated by examining technical details with examples of industrial products. The issues and development directions for future automotive power module packaging are also discussed.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129444166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229062
Hoon Chang, Jaejune Jang, Minhwan Kim, eung-Kyu Lee, D. Jang, Junsung Park, Jaehyeon Jung, Changjoon Yoon, Sung-Ryoul Bae, Chan Park
This paper presents BCD process integrating 7V to 70V power devices on 0.13um CMOS platform for various power management applications. BJT, Zener diode and Schottky diode are available and non-volatile memory is embedded as well. LDMOS shows best-in-class specific Ron (RSP) vs. BVDSS characteristics (i.e., 70V NMOS has RSP of 69mΩ-mm2 with BVDSS of 89V). Modular process scheme is used for flexibility to various requirements of applications.
{"title":"Advanced 0.13um smart power technology from 7V to 70V","authors":"Hoon Chang, Jaejune Jang, Minhwan Kim, eung-Kyu Lee, D. Jang, Junsung Park, Jaehyeon Jung, Changjoon Yoon, Sung-Ryoul Bae, Chan Park","doi":"10.1109/ISPSD.2012.6229062","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229062","url":null,"abstract":"This paper presents BCD process integrating 7V to 70V power devices on 0.13um CMOS platform for various power management applications. BJT, Zener diode and Schottky diode are available and non-volatile memory is embedded as well. LDMOS shows best-in-class specific Ron (R<sub>SP</sub>) vs. BV<sub>DSS</sub> characteristics (i.e., 70V NMOS has R<sub>SP</sub> of 69mΩ-mm<sup>2</sup> with BV<sub>DSS</sub> of 89V). Modular process scheme is used for flexibility to various requirements of applications.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114342098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229036
K. Bach, M. Asam, W. Kanert
In this paper we present a mechanism leading to early fails in a trench power MOSFET when operated at high drain currents under repetitive avalanche conditions (also referred to as “unclamped inductive switching”). While typical fails show burn marks at (or under) the bond stitches, early fails can occur close to the active area's edges or corners. With plausible assumptions both cases can be consistently explained by thermal runaway as demonstrated by electrothermal simulation.
{"title":"Failure mechanisms of low-voltage trench power MOSFETs under repetitive avalanche conditions","authors":"K. Bach, M. Asam, W. Kanert","doi":"10.1109/ISPSD.2012.6229036","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229036","url":null,"abstract":"In this paper we present a mechanism leading to early fails in a trench power MOSFET when operated at high drain currents under repetitive avalanche conditions (also referred to as “unclamped inductive switching”). While typical fails show burn marks at (or under) the bond stitches, early fails can occur close to the active area's edges or corners. With plausible assumptions both cases can be consistently explained by thermal runaway as demonstrated by electrothermal simulation.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114350296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229096
X. Perpiñà, I. Cortés, J. Urresti-Ibañez, X. Jordà, J. Rebollo, J. Millán
The clamped inductive turn-off failure of NPT-IGBTs is investigated under overloading events. First, their signatures are determined. Second, physical TCAD simulations are carried out considering, for the first time, the current mismatch among the cells from the chip core, gate runner and edge termination areas. As a result, a secondary breakdown at the IGBT peripheral cells at the edge of the gate runner has been indentified to be responsible of the failure. Besides, a strategy to enhance the device robustness is proposed.
{"title":"Clamped inductive turn-off failure in high-voltage NPT-IGBTs under overloading conditions","authors":"X. Perpiñà, I. Cortés, J. Urresti-Ibañez, X. Jordà, J. Rebollo, J. Millán","doi":"10.1109/ISPSD.2012.6229096","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229096","url":null,"abstract":"The clamped inductive turn-off failure of NPT-IGBTs is investigated under overloading events. First, their signatures are determined. Second, physical TCAD simulations are carried out considering, for the first time, the current mismatch among the cells from the chip core, gate runner and edge termination areas. As a result, a secondary breakdown at the IGBT peripheral cells at the edge of the gate runner has been indentified to be responsible of the failure. Besides, a strategy to enhance the device robustness is proposed.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"43 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114537354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229063
R. Su, C. C. Cheng, K. Huo, F. J. Yang, J. Tsai, R. Liou, H. Tuan
In this paper, a 700V lateral insulated gate bipolar transistor (LIGBT) design is proposed in a junction-isolated technology. Several key properties of LIGBT, such as hole injection leakage and breakdown-voltage, are investigated by using two-dimensional numerical simulator, MEDICI. To improve vertical junction isolation capability, an extra BLN (Buried-Layer N-type) layer is inserted in-between the BLP (Buried-Layer P-type) and the P-substrate, to enhance hole potential barrier and to block substrate leakage as well as to ensure high breakdown voltage (>;700V). An optimized LIGBT with high breakdown-voltage, very low substrate-leakage (<;0.1uA/um), and low switching turn-off time, are presented and analyzed.
{"title":"Design of 700V LIGBT with the suppressed substrate current in a 0.5um junction isolated technology","authors":"R. Su, C. C. Cheng, K. Huo, F. J. Yang, J. Tsai, R. Liou, H. Tuan","doi":"10.1109/ISPSD.2012.6229063","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229063","url":null,"abstract":"In this paper, a 700V lateral insulated gate bipolar transistor (LIGBT) design is proposed in a junction-isolated technology. Several key properties of LIGBT, such as hole injection leakage and breakdown-voltage, are investigated by using two-dimensional numerical simulator, MEDICI. To improve vertical junction isolation capability, an extra BLN (Buried-Layer N-type) layer is inserted in-between the BLP (Buried-Layer P-type) and the P-substrate, to enhance hole potential barrier and to block substrate leakage as well as to ensure high breakdown voltage (>;700V). An optimized LIGBT with high breakdown-voltage, very low substrate-leakage (<;0.1uA/um), and low switching turn-off time, are presented and analyzed.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124304543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229074
A. Nakajima, Y. Sumida, H. Kawai, V. Unni, K. Menon, M. H. Dhyani, E. Narayanan
GaN based bidirectional Super Heterojunction Field Effect Transistors (BiSHFETs) using the polarization junction (PJ) concept are demonstrated for the first time. The fabricated BiSHFETs are arrayed on an insulator substrate of Sapphire and measured isolation voltage between the devices is more than 2 kV. Measured on-resistances of the fabricated BiSHFETs with MES and PN gate structures are 24 Ωmm and 22 Ωmm in the both directions respectively.
{"title":"GaN-based bidirectional Super HFETs Using polarization junction concept on insulator substrate","authors":"A. Nakajima, Y. Sumida, H. Kawai, V. Unni, K. Menon, M. H. Dhyani, E. Narayanan","doi":"10.1109/ISPSD.2012.6229074","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229074","url":null,"abstract":"GaN based bidirectional Super Heterojunction Field Effect Transistors (BiSHFETs) using the polarization junction (PJ) concept are demonstrated for the first time. The fabricated BiSHFETs are arrayed on an insulator substrate of Sapphire and measured isolation voltage between the devices is more than 2 kV. Measured on-resistances of the fabricated BiSHFETs with MES and PN gate structures are 24 Ωmm and 22 Ωmm in the both directions respectively.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132033330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229072
S. Ryu, C. Capell, C. Jonas, Lin Cheng, M. O'loughlin, A. Burk, A. Agarwal, J. Palmour, A. Hefner
We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.
{"title":"Ultra high voltage (>12 kV), high performance 4H-SiC IGBTs","authors":"S. Ryu, C. Capell, C. Jonas, Lin Cheng, M. O'loughlin, A. Burk, A. Agarwal, J. Palmour, A. Hefner","doi":"10.1109/ISPSD.2012.6229072","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229072","url":null,"abstract":"We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 4H-SiC P-IGBT, with a chip size of 6.7 mm × 6.7 mm and an active area of 0.16 cm2 exhibited a record high blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 24 mΩ-cm2 with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. Buffer layer design, which includes controlling the doping concentration and the thickness of the field-stop buffer layers, was used to control the charge injection from the backside. Effects on buffer layer design on static characteristics and switching behavior are reported.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134328744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-03DOI: 10.1109/ISPSD.2012.6229065
W. Saito, Y. Saito, H. Fujimoto, A. Yoshioka, T. Ohno, T. Naka, T. Sugiyama
This paper reports that the switching controllability of high-voltage GaN-HEMTs and the cascode connection depends on the feedback capacitance design. The switching behavior of the GaN-HEMT can be controlled by the external gate resistance as the same manner as the conventional Si-MOSFETs. The switching controllability was improved by the substrate connection due to the parasitic capacitance change. The controllability of the cascode connection was slightly worse compared with the Si-MOSFET, because the effective feedback capacitance became small by the step by step switching operation.
{"title":"Switching controllability of high voltage GaN-HEMTs and the cascode connection","authors":"W. Saito, Y. Saito, H. Fujimoto, A. Yoshioka, T. Ohno, T. Naka, T. Sugiyama","doi":"10.1109/ISPSD.2012.6229065","DOIUrl":"https://doi.org/10.1109/ISPSD.2012.6229065","url":null,"abstract":"This paper reports that the switching controllability of high-voltage GaN-HEMTs and the cascode connection depends on the feedback capacitance design. The switching behavior of the GaN-HEMT can be controlled by the external gate resistance as the same manner as the conventional Si-MOSFETs. The switching controllability was improved by the substrate connection due to the parasitic capacitance change. The controllability of the cascode connection was slightly worse compared with the Si-MOSFET, because the effective feedback capacitance became small by the step by step switching operation.","PeriodicalId":371298,"journal":{"name":"2012 24th International Symposium on Power Semiconductor Devices and ICs","volume":"28 31","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132938301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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