{"title":"A hardware accelerator for H.264/AVC motion compensation","authors":"Haung-Chun Tseng, Cheng-Ru Chang, Y. Lin","doi":"10.1109/SIPS.2005.1579867","DOIUrl":null,"url":null,"abstract":"We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports all advanced features including variable-block-size motion estimation from multiple reference frames for both P and B slices, quarter-pixel accuracy, and weighted bi-directional prediction. We pay special attention to memory subsystem design for optimizing both memory usage and memory bandwidth. We have integrated the accelerator into an H.264/AVC main profile decoder in FPGA prototype. Compared with previous work, our accelerator is smaller and faster.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2005.1579867","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
We propose a hardware accelerator for H.264/AVC motion compensation. Our design supports all advanced features including variable-block-size motion estimation from multiple reference frames for both P and B slices, quarter-pixel accuracy, and weighted bi-directional prediction. We pay special attention to memory subsystem design for optimizing both memory usage and memory bandwidth. We have integrated the accelerator into an H.264/AVC main profile decoder in FPGA prototype. Compared with previous work, our accelerator is smaller and faster.
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