{"title":"Efficient design of symbol detector for MIMO-OFDM based wireless LANs","authors":"Seungpyo Noh, Yunho Jung, Jaeseok Kim","doi":"10.1109/ICTMICC.2007.4448690","DOIUrl":null,"url":null,"abstract":"In this paper, efficient hardware architecture for MIMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MIMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18 /spl mu/m CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTMICC.2007.4448690","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, efficient hardware architecture for MIMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MIMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18 /spl mu/m CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.
本文提出了一种具有双收发天线的MIMO-OFDM符号检测器的高效硬件结构。所提出的符号检测器支持SFBC-OFDM和SDM-OFDM两种MIMO-OFDM模式。由于两种MIMO-OFDM模式的检测算法相似，可以采用共享架构实现。因此，通过消除重复的功能块，可以实现低复杂度的实现。采用硬件描述语言设计，采用0.18 /spl μ m CMOS标准单元库合成门级电路。符号检测器的总逻辑门计数为164K。通过高效的硬件结构，所提出的符号检测器使逻辑门减少了34%，功耗减少了38%。
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