Pub Date : 2007-05-14DOI: 10.1109/ICTMICC.2007.4448690
Seungpyo Noh, Yunho Jung, Jaeseok Kim
In this paper, efficient hardware architecture for MIMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MIMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18 /spl mu/m CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.
本文提出了一种具有双收发天线的MIMO-OFDM符号检测器的高效硬件结构。所提出的符号检测器支持SFBC-OFDM和SDM-OFDM两种MIMO-OFDM模式。由于两种MIMO-OFDM模式的检测算法相似，可以采用共享架构实现。因此，通过消除重复的功能块，可以实现低复杂度的实现。采用硬件描述语言设计，采用0.18 /spl μ m CMOS标准单元库合成门级电路。符号检测器的总逻辑门计数为164K。通过高效的硬件结构，所提出的符号检测器使逻辑门减少了34%，功耗减少了38%。
{"title":"Efficient design of symbol detector for MIMO-OFDM based wireless LANs","authors":"Seungpyo Noh, Yunho Jung, Jaeseok Kim","doi":"10.1109/ICTMICC.2007.4448690","DOIUrl":"https://doi.org/10.1109/ICTMICC.2007.4448690","url":null,"abstract":"In this paper, efficient hardware architecture for MIMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MIMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18 /spl mu/m CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123830386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-01DOI: 10.1109/SIPS.2005.1579876
Ye Li, B. Bakkaloglu, C. Chakrabarti
As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However due to dynamic range limitations, power supply and power consumption of the RF front-ends and analog sections do not scale in the same fashion. In fact, in scaled systems, the RF section of a wireless transceiver consumes more energy than the digital part. For better understanding of the design trade offs, we first develop an accurate and comprehensive energy model for the analog front-end of wireless transceivers. Next, we evaluate a single user point-to-point wireless data communication system and a multi-user CDMA based system with respect to RF front end energy consumption and communication quality. We demonstrate the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping roll-off factor on single user system, and the effect of number of users and multiple access interference (MAI) on CDMA based multi-user system. For a given quality specification, we show how the energy consumption can be reduced by adjusting one or more of these parameters.
{"title":"A comprehensive energy model and energy-quality evaluation of wireless transceiver front-ends","authors":"Ye Li, B. Bakkaloglu, C. Chakrabarti","doi":"10.1109/SIPS.2005.1579876","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579876","url":null,"abstract":"As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However due to dynamic range limitations, power supply and power consumption of the RF front-ends and analog sections do not scale in the same fashion. In fact, in scaled systems, the RF section of a wireless transceiver consumes more energy than the digital part. For better understanding of the design trade offs, we first develop an accurate and comprehensive energy model for the analog front-end of wireless transceivers. Next, we evaluate a single user point-to-point wireless data communication system and a multi-user CDMA based system with respect to RF front end energy consumption and communication quality. We demonstrate the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping roll-off factor on single user system, and the effect of number of users and multiple access interference (MAI) on CDMA based multi-user system. For a given quality specification, we show how the energy consumption can be reduced by adjusting one or more of these parameters.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128380714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-01DOI: 10.1109/SIPS.2005.1579900
A. Beric, B. van der Waal, R. Sethuraman, G. de Haan
In the domain of motion estimation based applications, in order to keep the bandwidth requirements low, the usage of multiple levels of memory hierarchy is a necessity. We analyze and optimize the two-level memory hierarchy system for motion estimation where the first level (L0 scratchpad) holds the search area of the estimator and the second level (L1 scratchpad) holds the region wherein the estimation is performed. In our system, the L1 scratchpad is reconfigurable and the aspect ratio of the region dynamically changes per video field. The aspect ratio is changed such that physically available region (L1) memory is maximally utilized. We extend this idea to the extreme case where the aspect ratio of the region changes from horizontal stripe to vertical column. This idea keeps the bandwidth requirements towards the off-chip image memory minimal, one access per pixel, regardless of the number of motion estimation scans. Further, switching the aspect ratio of the region to extreme values enables fast convergence of the motion estimator. To demonstrate our idea, experiments were performed on the test set of video sequences using the state-of-the-art de-interlacing as the application. The results are encouraging regarding both, objective quality metric as well as visual perception.
{"title":"Low-bandwidth dynamic aspect ratio region-based motion estimation","authors":"A. Beric, B. van der Waal, R. Sethuraman, G. de Haan","doi":"10.1109/SIPS.2005.1579900","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579900","url":null,"abstract":"In the domain of motion estimation based applications, in order to keep the bandwidth requirements low, the usage of multiple levels of memory hierarchy is a necessity. We analyze and optimize the two-level memory hierarchy system for motion estimation where the first level (L0 scratchpad) holds the search area of the estimator and the second level (L1 scratchpad) holds the region wherein the estimation is performed. In our system, the L1 scratchpad is reconfigurable and the aspect ratio of the region dynamically changes per video field. The aspect ratio is changed such that physically available region (L1) memory is maximally utilized. We extend this idea to the extreme case where the aspect ratio of the region changes from horizontal stripe to vertical column. This idea keeps the bandwidth requirements towards the off-chip image memory minimal, one access per pixel, regardless of the number of motion estimation scans. Further, switching the aspect ratio of the region to extreme values enables fast convergence of the motion estimator. To demonstrate our idea, experiments were performed on the test set of video sequences using the state-of-the-art de-interlacing as the application. The results are encouraging regarding both, objective quality metric as well as visual perception.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-01DOI: 10.1109/SIPS.2005.1579938
T. Hsiao, Chien-Ching Lin, Hsie-Chia Chang
An application specific digital signal processor for channel coding is presented. The vector operations can improve both the performance of memory accesses and program code density. The special function units and datapaths for channel decoding accelerate the decoding speed and facilitate algorithm implementation. The processor had been fabricated in a 0.18 /spl mu/m CMOS 1P6M technology. The chip size is 7.73 mm/sup 2/ including 18k bits embedded memory, and the power consumption is 141 mW while decoding Reed-Solomon code and convolutional code. In contrast with general purpose processor designs, the results show this chip has at least 50% improvement in code density and 66% data rate enhancement.
提出了一种专用于信道编码的数字信号处理器。向量操作可以提高内存访问性能和程序代码密度。信道译码的特殊功能单元和数据路径加快了译码速度，便于算法实现。该处理器采用0.18 /spl μ m CMOS 1P6M工艺制造。芯片尺寸为7.73 mm/sup 2/，包括18k位嵌入式存储器，解码里德-所罗门码和卷积码时功耗为141 mW。结果表明，与通用处理器设计相比，该芯片的代码密度至少提高了50%，数据速率提高了66%。
{"title":"An AS-DSP for forward error correction applications","authors":"T. Hsiao, Chien-Ching Lin, Hsie-Chia Chang","doi":"10.1109/SIPS.2005.1579938","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579938","url":null,"abstract":"An application specific digital signal processor for channel coding is presented. The vector operations can improve both the performance of memory accesses and program code density. The special function units and datapaths for channel decoding accelerate the decoding speed and facilitate algorithm implementation. The processor had been fabricated in a 0.18 /spl mu/m CMOS 1P6M technology. The chip size is 7.73 mm/sup 2/ including 18k bits embedded memory, and the power consumption is 141 mW while decoding Reed-Solomon code and convolutional code. In contrast with general purpose processor designs, the results show this chip has at least 50% improvement in code density and 66% data rate enhancement.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130929364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a dynamic normalization technique is proposed to approximate the nonlinear operation in decoding LDPC codes. The criterion in determining the normalization factor is also presented with theoretical analysis. The proposed method improves the approximation accuracy as well as the error performance of min-sum algorithm. Furthermore, the hardware implementation benefits from a simplified normalization scheme, leading to reductions in complexity and implementation loss.
{"title":"A dynamic normalization technique for decoding LDPC codes","authors":"Yen-Chin Liao, Chien-Ching Lin, Chih-Wei Liu, Hsie-Chia Chang","doi":"10.1109/SIPS.2005.1579968","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579968","url":null,"abstract":"In this paper, a dynamic normalization technique is proposed to approximate the nonlinear operation in decoding LDPC codes. The criterion in determining the normalization factor is also presented with theoretical analysis. The proposed method improves the approximation accuracy as well as the error performance of min-sum algorithm. Furthermore, the hardware implementation benefits from a simplified normalization scheme, leading to reductions in complexity and implementation loss.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122022899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-01DOI: 10.1109/SIPS.2005.1579929
Tuanjie Qian, Jun Sun, Rong Xie, Pengcheng Su, Jia Wang, Xiaokang Yang
A new scheme combining a scalable transcoder with space time block codes (STBC) for an orthogonal frequency division multiplexing (OFDM) system is proposed for robust video transmission in dispersive fading channels. The target application for such a scalable transcoder is to provide successful access to the pre-encoded high quality video from mobile wireless terminals. In the scalable transcoder, besides outputting the fine granular scalability (FGS) bitstream, both size of video frames and the bit rate are reduced. And an array processing algorithm of layer interference suppression is used at the receiver which makes the system structure provide different levels of protection to different layers. Furthermore, by considering the important level of scalable bitstream, the different bitstreams can be given different level protection by the system structure and channel coding. With the proposed system, the concurrent large diversity gain characteristic of STBC and alleviating the frequency-selective fading effect of OFDM can be achieved. The simulation results suggest that the proposed schemes integrating scalable transcoding can provide a basic quality of video transmission and outperform the convention single layer transcoding transmitted under the random and bursty error channel conditions.
{"title":"Scalable transcoding for video transmission over space-time OFDM systems","authors":"Tuanjie Qian, Jun Sun, Rong Xie, Pengcheng Su, Jia Wang, Xiaokang Yang","doi":"10.1109/SIPS.2005.1579929","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579929","url":null,"abstract":"A new scheme combining a scalable transcoder with space time block codes (STBC) for an orthogonal frequency division multiplexing (OFDM) system is proposed for robust video transmission in dispersive fading channels. The target application for such a scalable transcoder is to provide successful access to the pre-encoded high quality video from mobile wireless terminals. In the scalable transcoder, besides outputting the fine granular scalability (FGS) bitstream, both size of video frames and the bit rate are reduced. And an array processing algorithm of layer interference suppression is used at the receiver which makes the system structure provide different levels of protection to different layers. Furthermore, by considering the important level of scalable bitstream, the different bitstreams can be given different level protection by the system structure and channel coding. With the proposed system, the concurrent large diversity gain characteristic of STBC and alleviating the frequency-selective fading effect of OFDM can be achieved. The simulation results suggest that the proposed schemes integrating scalable transcoding can provide a basic quality of video transmission and outperform the convention single layer transcoding transmitted under the random and bursty error channel conditions.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"430 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116002933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-02DOI: 10.1109/SIPS.2005.1579941
N. Hervé, D. Ménard, O. Sentieys
Field programmable gate arrays (FPGAs) are now considered as a real alternative for digital signal processing (DSP) applications. But, new methodologies are still needed to automatically map a DSP application into an FPGA with respect to design constraints such as area, power consumption, execution time and time-to-market. Moreover DSP applications are frequently specified using floating-point arithmetic whereas fixed-point arithmetic should be used on FPGA. In this paper, a high-level synthesis methodology under constraints is presented. The originality is to consider a computation accuracy constraint. The methodology is based on a fixed-point operator library which characterizes the operators cost according to their wordlength. An error noise propagation model is used to compute an analytical expression of the accuracy in function of the signals wordlength. To obtain an efficient hardware implementation, the data wordlength optimization process is coupled with the high-level synthesis. In addition, the accuracy evaluation is done through an analytical method, which drastically reduces the optimization time.
{"title":"Data wordlength optimization for FPGA synthesis","authors":"N. Hervé, D. Ménard, O. Sentieys","doi":"10.1109/SIPS.2005.1579941","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579941","url":null,"abstract":"Field programmable gate arrays (FPGAs) are now considered as a real alternative for digital signal processing (DSP) applications. But, new methodologies are still needed to automatically map a DSP application into an FPGA with respect to design constraints such as area, power consumption, execution time and time-to-market. Moreover DSP applications are frequently specified using floating-point arithmetic whereas fixed-point arithmetic should be used on FPGA. In this paper, a high-level synthesis methodology under constraints is presented. The originality is to consider a computation accuracy constraint. The methodology is based on a fixed-point operator library which characterizes the operators cost according to their wordlength. An error noise propagation model is used to compute an analytical expression of the accuracy in function of the signals wordlength. To obtain an efficient hardware implementation, the data wordlength optimization process is coupled with the high-level synthesis. In addition, the accuracy evaluation is done through an analytical method, which drastically reduces the optimization time.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126553720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-02DOI: 10.1109/SIPS.2005.1579937
H. Jégou, S. Malinowski, C. Guillemot
This paper describes a new set of state models for soft decoding of variable length codes. A single parameter T allows to trade complexity against estimation accuracy. The extrema choices for this parameter lead respectively to construct the well-known bit-level and bit/symbol trellises. For a proper choice of the parameter T, the results obtained by running a BCJR or Viterbi estimation algorithm on the proposed state models are close to those obtained with the optimum state model. The complexity is however significantly reduced. It can be further decreased by projecting the state model on two state models of reduced size, and by combining their decoding results. This combination is shown to be optimal for the Viterbi algorithm.
{"title":"Trellis state aggregation for soft decoding of variable length codes","authors":"H. Jégou, S. Malinowski, C. Guillemot","doi":"10.1109/SIPS.2005.1579937","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579937","url":null,"abstract":"This paper describes a new set of state models for soft decoding of variable length codes. A single parameter T allows to trade complexity against estimation accuracy. The extrema choices for this parameter lead respectively to construct the well-known bit-level and bit/symbol trellises. For a proper choice of the parameter T, the results obtained by running a BCJR or Viterbi estimation algorithm on the proposed state models are close to those obtained with the optimum state model. The complexity is however significantly reduced. It can be further decreased by projecting the state model on two state models of reduced size, and by combining their decoding results. This combination is shown to be optimal for the Viterbi algorithm.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114893218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-02DOI: 10.1109/SIPS.2005.1579931
V. Chouliaras, J. Flint, Yibin Li, J. Núñez-Yáñez
We discuss a configurable, system-on-chip vector multiprocessor for accelerating the transmission line modeling (TLM) algorithm with an architecture capable of exploiting the two primary forms of parallelism in the code, thread and data level parallelism. Theoretical results demonstrate an order of magnitude reduction in the dynamic instruction count for a scalar-processor/vector-coprocessor configuration at a vector length of sixteen 32-bit single-precision elements. Furthermore, a multi-vector SoC architecture consisting of ten such vector accelerators provides a near-linear theoretical performance benefit of the order of 88% in three out of four benchmark configurations which is orthogonal to the benefit realized by vectorization alone. We discuss in detail this potent architecture and present implementation data for the 2-way multi-processor VLSI macrocell.
{"title":"A system-on-chip vector multiprocessor for transmission line modelling acceleration","authors":"V. Chouliaras, J. Flint, Yibin Li, J. Núñez-Yáñez","doi":"10.1109/SIPS.2005.1579931","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579931","url":null,"abstract":"We discuss a configurable, system-on-chip vector multiprocessor for accelerating the transmission line modeling (TLM) algorithm with an architecture capable of exploiting the two primary forms of parallelism in the code, thread and data level parallelism. Theoretical results demonstrate an order of magnitude reduction in the dynamic instruction count for a scalar-processor/vector-coprocessor configuration at a vector length of sixteen 32-bit single-precision elements. Furthermore, a multi-vector SoC architecture consisting of ten such vector accelerators provides a near-linear theoretical performance benefit of the order of 88% in three out of four benchmark configurations which is orthogonal to the benefit realized by vectorization alone. We discuss in detail this potent architecture and present implementation data for the 2-way multi-processor VLSI macrocell.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117231518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-02DOI: 10.1109/SIPS.2005.1579947
Jing Zhang, A. Ho
A novel grayscale watermark pre-processing and a robust video watermarking algorithm for the emerging video coding standard H.264/AVC are proposed in this paper for the copyright protection application. This algorithm can insert grayscale watermark patterns such as detailed trademarks or logos into the low bit-rate H.264/AVC videos in the compressed domain with good robustness and high capacity. The marked video sequences maintain good visual quality and the same overall consuming bit-rate. The proposed algorithm can robustly survive transcoding process and common signal processing, such as bit-rate reduction, Gaussian filtering and contrast enhancement.
{"title":"Robust digital image-in-video watermarking for the emerging H.264/AVC standard","authors":"Jing Zhang, A. Ho","doi":"10.1109/SIPS.2005.1579947","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579947","url":null,"abstract":"A novel grayscale watermark pre-processing and a robust video watermarking algorithm for the emerging video coding standard H.264/AVC are proposed in this paper for the copyright protection application. This algorithm can insert grayscale watermark patterns such as detailed trademarks or logos into the low bit-rate H.264/AVC videos in the compressed domain with good robustness and high capacity. The marked video sequences maintain good visual quality and the same overall consuming bit-rate. The proposed algorithm can robustly survive transcoding process and common signal processing, such as bit-rate reduction, Gaussian filtering and contrast enhancement.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124341885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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