Y. Kaneko, H. Shimizu, K. Nagata, M. Koyanagi, M. Okamoto, M. Suzuki, S. Yokokawa, S. Shimizu, T. Maejima, J. Wada, H. Kawada, S. Ueno, M. Minamizawa, I. Yaegashi
{"title":"A 25 k-gate BDCFL G/A with a differential push-pull ECL I/O","authors":"Y. Kaneko, H. Shimizu, K. Nagata, M. Koyanagi, M. Okamoto, M. Suzuki, S. Yokokawa, S. Shimizu, T. Maejima, J. Wada, H. Kawada, S. Ueno, M. Minamizawa, I. Yaegashi","doi":"10.1109/GAAS.1993.394483","DOIUrl":null,"url":null,"abstract":"The authors develop a 25 k-gate array with 0.8-/spl mu/m buried p-layer MESFET, three-level gold-based interconnects, and Au bump technology. They use differential push-pull circuits for the ECL interface circuits to obtain a sufficient margin, a low-voltage (-1.6 V) power supply for the internal gates to reduce the power consumption, and -2.0 V for the I/O circuits. The basic cell array combines DCFL and ECL compatible buffered DCFL gates (BDCFL). The basic delay times are 45 ps for 0.75 mW DCFL and 60 ps for 1.2 mW BDCFL gates. The gate array chip size is 10.7/spl times/10/7 mm, and contains 24,320 three-input BDCFL internal gates. The authors also use 80 /spl mu/m TAB to reduce the package delay time and simultaneous switching output noise. They use the array in a vector parallel processor which has a peak performance of 355 GFLOPS.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th Annual GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1993.394483","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The authors develop a 25 k-gate array with 0.8-/spl mu/m buried p-layer MESFET, three-level gold-based interconnects, and Au bump technology. They use differential push-pull circuits for the ECL interface circuits to obtain a sufficient margin, a low-voltage (-1.6 V) power supply for the internal gates to reduce the power consumption, and -2.0 V for the I/O circuits. The basic cell array combines DCFL and ECL compatible buffered DCFL gates (BDCFL). The basic delay times are 45 ps for 0.75 mW DCFL and 60 ps for 1.2 mW BDCFL gates. The gate array chip size is 10.7/spl times/10/7 mm, and contains 24,320 three-input BDCFL internal gates. The authors also use 80 /spl mu/m TAB to reduce the package delay time and simultaneous switching output noise. They use the array in a vector parallel processor which has a peak performance of 355 GFLOPS.<>
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