Heterogeneously encoded dual-bit self-timed adder

Abstract

A novel heterogeneously encoded dual-bit self-timed adder design is presented in this paper. Heterogeneous encoding refers to a combination of at least two different delay-insensitive encoding schemes, adopted for the inputs and outputs. The primary motivation being that higher order 1-of-n encoding protocols facilitate reduction in terms of the circuit switching power dissipation compared to the basic dual-rail (1-of-2, which is the simplest 1-of-n code) encoding scheme. Here, n specifies the number of physical lines. The number of transitions gets reduced by O(k) over a dual-rail code, with k being the number of primary inputs and equals log2n. The design of a dual-bit adder is considered to illustrate the advantage of the heterogeneous encoding scheme. The proposed adder design satisfies Seitz's weak-indication timing constraints. In comparison with dual-bit adders realized using other approaches, employing dual-rail encoding or heterogeneous encoding, the proposed design is found to be efficient in terms of delay, power consumption and area parameters.