New physical insight for analog application in PSP bulk compact model

Abstract

With the maturity of CMOS technologies and their use for low voltage analog applications, some additional parasitic effects must be modeled to improve again the accuracy of SPICE models. Indeed, with the decrease of supply voltage, devices operate close to the weak inversion, where some effects such as parasitic sidewall transistor, also called hump effect [1], and the interface states effect [2], can have a significant impact on the model accuracy. This paper describes the latest significant improvements of PSP model related to version 103.6 including new compact models of parasitic MOSFET and interface states. The major challenge is to provide accurate solutions with a low impact on CPU times for large analog circuit designs. The model extensions are validated against Silicon experiments from devices with channel length down to 40nm, and including low voltage and body bias operation.